| Message ID | 1363973369-26110-25-git-send-email-yorksun@freescale.com |
|---|---|
| State | Superseded |
| Headers | show |
Dear York Sun, In message <1363973369-26110-25-git-send-email-yorksun@freescale.com> you wrote: > From: Shaohui Xie <Shaohui.Xie@freescale.com> > > PC board has different serdes clock setting with PB board, it uses same > serdes frequency setting on bank2 as on bank1. PC board can be distingushed > from PB board by checking CPLD version, if running on PC board, then fix > the serdes reference clock frequency of bank2. > > Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> > --- > board/freescale/p2041rdb/p2041rdb.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) CHECK: Logical continuations should be on the previous line #134: FILE: board/freescale/p2041rdb/p2041rdb.c:237: + if ((i == 1) && (CPLD_READ(cpld_ver_sub) == 1) + && (CPLD_READ(pcba_ver) == 5)) { Best regards, Wolfgang Denk
diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c index a706a6d..9352fab 100644 --- a/board/freescale/p2041rdb/p2041rdb.c +++ b/board/freescale/p2041rdb/p2041rdb.c @@ -227,6 +227,17 @@ int misc_init_r(void) "'00' is unsupported\n"); else actual[i] = freq[i][clock]; + + /* + * PC board uses a different CPLD with PB board, this CPLD + * has cpld_ver_sub = 1, and pcba_ver = 5. But CPLD on PB + * board has cpld_ver_sub = 0, and pcba_ver = 4. + */ + if ((i == 1) && (CPLD_READ(cpld_ver_sub) == 1) + && (CPLD_READ(pcba_ver) == 5)) { + /* PC board bank2 frequency */ + actual[i] = freq[i-1][clock]; + } } for (i = 0; i < NUM_SRDS_BANKS; i++) {