From patchwork Fri Mar 22 17:24:05 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: York Sun X-Patchwork-Id: 230167 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 788B32C00B6 for ; Sat, 23 Mar 2013 04:27:05 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 19BBA4A0B3; Fri, 22 Mar 2013 18:26:34 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id vl7qlgXfaFt4; Fri, 22 Mar 2013 18:26:33 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 37EE14A184; Fri, 22 Mar 2013 18:25:07 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E17AF4A143 for ; Fri, 22 Mar 2013 18:25:00 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id fo4owe4W7KPV for ; Fri, 22 Mar 2013 18:25:00 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from co9outboundpool.messaging.microsoft.com (co9ehsobe004.messaging.microsoft.com [207.46.163.27]) by theia.denx.de (Postfix) with ESMTPS id 0C4974A154 for ; Fri, 22 Mar 2013 18:24:34 +0100 (CET) Received: from mail20-co9-R.bigfish.com (10.236.132.233) by CO9EHSOBE032.bigfish.com (10.236.130.95) with Microsoft SMTP Server id 14.1.225.23; Fri, 22 Mar 2013 17:24:32 +0000 Received: from mail20-co9 (localhost [127.0.0.1]) by mail20-co9-R.bigfish.com (Postfix) with ESMTP id 77E70600C3 for ; Fri, 22 Mar 2013 17:24:32 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1f42h1ee6h1de0h1202h1e76h1d1ah1d2ahzz8275bhz2dh2a8h668h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1155h) Received: from mail20-co9 (localhost.localdomain [127.0.0.1]) by mail20-co9 (MessageSwitch) id 1363973070360323_32526; Fri, 22 Mar 2013 17:24:30 +0000 (UTC) Received: from CO9EHSMHS005.bigfish.com (unknown [10.236.132.235]) by mail20-co9.bigfish.com (Postfix) with ESMTP id 4B35A3A010C for ; Fri, 22 Mar 2013 17:24:30 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CO9EHSMHS005.bigfish.com (10.236.130.15) with Microsoft SMTP Server (TLS) id 14.1.225.23; Fri, 22 Mar 2013 17:24:27 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-001.039d.mgd.msft.net (10.84.1.13) with Microsoft SMTP Server (TLS) id 14.2.328.11; Fri, 22 Mar 2013 17:24:26 +0000 Received: from oslab-l1.am.freescale.net ([10.214.84.93]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id r2MHOET8017745; Fri, 22 Mar 2013 10:24:24 -0700 From: York Sun To: Date: Fri, 22 Mar 2013 10:24:05 -0700 Message-ID: <1363973052-25918-12-git-send-email-yorksun@freescale.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1363973052-25918-1-git-send-email-yorksun@freescale.com> References: <1363973052-25918-1-git-send-email-yorksun@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com Cc: u-boot@lists.denx.de, York Sun Subject: [U-Boot] [PATCH 14/21] powerpc/b4860qds: Assign DDR address in board file X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de B4860QDS requires DDRC2 has 0 as base address and DDRC1 has higher address. This is the requirement for DSP cores to run in 32-bit address space. Signed-off-by: York Sun --- board/freescale/b4860qds/ddr.c | 72 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c index dd4c0f6..f19f338 100644 --- a/board/freescale/b4860qds/ddr.c +++ b/board/freescale/b4860qds/ddr.c @@ -13,6 +13,7 @@ #include #include #include +#include <../arch/powerpc/cpu/mpc8xxx/ddr/ddr.h> DECLARE_GLOBAL_DATA_PTR; @@ -188,3 +189,74 @@ phys_size_t initdram(int board_type) puts(" DDR: "); return dram_size; } + +unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo, + unsigned int dbw_cap_adj[]) +{ + int i, j; + unsigned long long total_mem, current_mem_base, total_ctlr_mem; + unsigned long long rank_density, ctlr_density = 0; + + current_mem_base = 0ull; + total_mem = 0; + /* + * This board has soldered DDR chips. DDRC1 has two rank. + * DDRC2 has only one rank. + * Assigning DDRC2 to lower address and DDRC1 to higher address. + */ + if (pinfo->memctl_opts[0].memctl_interleaving) { + rank_density = pinfo->dimm_params[0][0].rank_density >> + dbw_cap_adj[0]; + ctlr_density = rank_density; + + debug("rank density is 0x%llx, ctlr density is 0x%llx\n", + rank_density, ctlr_density); + for (i = CONFIG_NUM_DDR_CONTROLLERS - 1; i >= 0; i--) { + switch (pinfo->memctl_opts[i].memctl_interleaving_mode) { + case FSL_DDR_CACHE_LINE_INTERLEAVING: + case FSL_DDR_PAGE_INTERLEAVING: + case FSL_DDR_BANK_INTERLEAVING: + case FSL_DDR_SUPERBANK_INTERLEAVING: + total_ctlr_mem = 2 * ctlr_density; + break; + default: + panic("Unknown interleaving mode"); + } + pinfo->common_timing_params[i].base_address = + current_mem_base; + pinfo->common_timing_params[i].total_mem = + total_ctlr_mem; + total_mem = current_mem_base + total_ctlr_mem; + debug("ctrl %d base 0x%llx\n", i, current_mem_base); + debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); + } + } else { + /* + * Simple linear assignment if memory + * controllers are not interleaved. + */ + for (i = CONFIG_NUM_DDR_CONTROLLERS - 1; i >= 0; i--) { + total_ctlr_mem = 0; + pinfo->common_timing_params[i].base_address = + current_mem_base; + for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { + /* Compute DIMM base addresses. */ + unsigned long long cap = + pinfo->dimm_params[i][j].capacity; + pinfo->dimm_params[i][j].base_address = + current_mem_base; + debug("ctrl %d dimm %d base 0x%llx\n", + i, j, current_mem_base); + current_mem_base += cap; + total_ctlr_mem += cap; + } + debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); + pinfo->common_timing_params[i].total_mem = + total_ctlr_mem; + total_mem += total_ctlr_mem; + } + } + debug("Total mem by %s is 0x%llx\n", __func__, total_mem); + + return total_mem; +}