From patchwork Tue Feb 12 11:33:45 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: SRICHARAN R X-Patchwork-Id: 219809 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 569B72C007B for ; Tue, 12 Feb 2013 22:35:06 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E75D04A092; Tue, 12 Feb 2013 12:34:58 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 9F6kbHaI-Vl1; Tue, 12 Feb 2013 12:34:58 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 92D8C4A09F; Tue, 12 Feb 2013 12:34:32 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4BB564A092 for ; Tue, 12 Feb 2013 12:34:26 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id I+I-KxTEAh-w for ; Tue, 12 Feb 2013 12:34:24 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from devils.ext.ti.com (devils.ext.ti.com [198.47.26.153]) by theia.denx.de (Postfix) with ESMTPS id 7563A4A087 for ; Tue, 12 Feb 2013 12:34:19 +0100 (CET) Received: from dbdp20.itg.ti.com ([172.24.170.38]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id r1CBYGYt008381 for ; Tue, 12 Feb 2013 05:34:17 -0600 Received: from DBDE71.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id r1CBYFqY000050 for ; Tue, 12 Feb 2013 17:04:15 +0530 (IST) Received: from dbdp33.itg.ti.com (172.24.170.252) by DBDE71.ent.ti.com (172.24.170.149) with Microsoft SMTP Server id 14.1.323.3; Tue, 12 Feb 2013 17:04:15 +0530 Received: from localhost.localdomain (smtpvbd.itg.ti.com [172.24.170.250]) by dbdp33.itg.ti.com (8.13.8/8.13.8) with ESMTP id r1CBY6FN021603; Tue, 12 Feb 2013 17:04:15 +0530 From: R Sricharan To: Date: Tue, 12 Feb 2013 17:03:45 +0530 Message-ID: <1360668825-15798-6-git-send-email-r.sricharan@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1360668825-15798-1-git-send-email-r.sricharan@ti.com> References: <1360668825-15798-1-git-send-email-r.sricharan@ti.com> MIME-Version: 1.0 Cc: Tom Rini Subject: [U-Boot] [PATCH V3 5/5] ARM: OMAP5: srcomp: enable slew rate compensation cells after powerup X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Lokesh Vutla After power-up SRCOMP cells are by-passed by default in OMAP5. Software has to enable these SRCOMP sells. For ES2: All 5 SRCOMP cells needs to be enabled. For ES1: Only 4 SRCOMP cells in core power domain are enabled. The 1 in wkup domain is not enabled because smart i/os of wkup domain work with default compensation code. Signed-off-by: R Sricharan Signed-off-by: Lokesh Vutla Reviewed-by: Tom Rini Cc: Tom Rini --- [v2] Addressed Tom Rini's comments [v3] No Change arch/arm/cpu/armv7/omap-common/hwinit-common.c | 6 ++ arch/arm/cpu/armv7/omap5/hwinit.c | 116 ++++++++++++++++++++++++ arch/arm/cpu/armv7/omap5/prcm-regs.c | 5 +- arch/arm/include/asm/arch-omap5/clocks.h | 4 + arch/arm/include/asm/arch-omap5/omap.h | 19 ++++ arch/arm/include/asm/arch-omap5/sys_proto.h | 1 + arch/arm/include/asm/omap_common.h | 2 + 7 files changed, 152 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index e5a5eb6..60af7eb 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -33,6 +33,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -100,6 +101,10 @@ void spl_display_print(void) } #endif +void __weak srcomp_enable(void) +{ +} + /* * Routine: s_init * Description: Does early system init of watchdog, muxing, andclocks @@ -126,6 +131,7 @@ void s_init(void) watchdog_init(); set_mux_conf_regs(); #ifdef CONFIG_SPL_BUILD + srcomp_enable(); setup_clocks_for_console(); gd = &gdata; diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index 8e66a96..f083198 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #include @@ -182,6 +183,121 @@ void do_io_settings(void) writel(EFUSE_3, (*ctrl)->control_efuse_3); writel(EFUSE_4, (*ctrl)->control_efuse_4); } + +static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = { + {0x45, 0x1}, /* 12 MHz */ + {-1, -1}, /* 13 MHz */ + {0x63, 0x2}, /* 16.8 MHz */ + {0x57, 0x2}, /* 19.2 MHz */ + {0x20, 0x1}, /* 26 MHz */ + {-1, -1}, /* 27 MHz */ + {0x41, 0x3} /* 38.4 MHz */ +}; + +void srcomp_enable(void) +{ + u32 srcomp_value, mul_factor, div_factor, clk_val, i; + u32 sysclk_ind = get_sys_clk_index(); + u32 omap_rev = omap_revision(); + + mul_factor = srcomp_parameters[sysclk_ind].multiply_factor; + div_factor = srcomp_parameters[sysclk_ind].divide_factor; + + for (i = 0; i < 4; i++) { + srcomp_value = readl((*ctrl)->control_srcomp_north_side + i*4); + srcomp_value &= + ~(MULTIPLY_FACTOR_XS_MASK | DIVIDE_FACTOR_XS_MASK); + srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) | + (div_factor << DIVIDE_FACTOR_XS_SHIFT); + writel(srcomp_value, (*ctrl)->control_srcomp_north_side + i*4); + } + + if ((omap_rev == OMAP5430_ES1_0) || (omap_rev == OMAP5432_ES1_0)) { + clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl); + clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK; + writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl); + + for (i = 0; i < 4; i++) { + srcomp_value = + readl((*ctrl)->control_srcomp_north_side + i*4); + srcomp_value &= ~PWRDWN_XS_MASK; + writel(srcomp_value, + (*ctrl)->control_srcomp_north_side + i*4); + + while (((readl((*ctrl)->control_srcomp_north_side + i*4) + & SRCODE_READ_XS_MASK) >> + SRCODE_READ_XS_SHIFT) == 0) + ; + + srcomp_value = + readl((*ctrl)->control_srcomp_north_side + i*4); + srcomp_value &= ~OVERRIDE_XS_MASK; + writel(srcomp_value, + (*ctrl)->control_srcomp_north_side + i*4); + } + } else { + srcomp_value = readl((*ctrl)->control_srcomp_east_side_wkup); + srcomp_value &= ~(MULTIPLY_FACTOR_XS_MASK | + DIVIDE_FACTOR_XS_MASK); + srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) | + (div_factor << DIVIDE_FACTOR_XS_SHIFT); + writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup); + + for (i = 0; i < 4; i++) { + srcomp_value = + readl((*ctrl)->control_srcomp_north_side + i*4); + srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK; + writel(srcomp_value, + (*ctrl)->control_srcomp_north_side + i*4); + + srcomp_value = + readl((*ctrl)->control_srcomp_north_side + i*4); + srcomp_value &= ~OVERRIDE_XS_MASK; + writel(srcomp_value, + (*ctrl)->control_srcomp_north_side + i*4); + } + + srcomp_value = + readl((*ctrl)->control_srcomp_east_side_wkup); + srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK; + writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup); + + srcomp_value = + readl((*ctrl)->control_srcomp_east_side_wkup); + srcomp_value &= ~OVERRIDE_XS_MASK; + writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup); + + clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl); + clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK; + writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl); + + clk_val = readl((*prcm)->cm_wkupaon_io_srcomp_clkctrl); + clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK; + writel(clk_val, (*prcm)->cm_wkupaon_io_srcomp_clkctrl); + + for (i = 0; i < 4; i++) { + while (((readl((*ctrl)->control_srcomp_north_side + i*4) + & SRCODE_READ_XS_MASK) >> + SRCODE_READ_XS_SHIFT) == 0) + ; + + srcomp_value = + readl((*ctrl)->control_srcomp_north_side + i*4); + srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK; + writel(srcomp_value, + (*ctrl)->control_srcomp_north_side + i*4); + } + + while (((readl((*ctrl)->control_srcomp_east_side_wkup) & + SRCODE_READ_XS_MASK) >> SRCODE_READ_XS_SHIFT) == 0) + ; + + srcomp_value = + readl((*ctrl)->control_srcomp_east_side_wkup); + srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK; + writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup); + } +} #endif void config_data_eye_leveling_samples(u32 emif_base) diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index 58c9d50..5e5abcc 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -149,6 +149,7 @@ struct prcm_regs const omap5_es1_prcm = { /* cm2.core */ .cm_coreaon_bandgap_clkctrl = 0x4a008648, + .cm_coreaon_io_srcomp_clkctrl = 0x4a008650, .cm_l3_1_clkstctrl = 0x4a008700, .cm_l3_1_dynamicdep = 0x4a008708, .cm_l3_1_l3_1_clkctrl = 0x4a008720, @@ -294,6 +295,7 @@ struct prcm_regs const omap5_es1_prcm = { .cm_wkup_rtc_clkctrl = 0x4ae07880, .cm_wkup_bandgap_clkctrl = 0x4ae07888, .cm_wkupaon_scrm_clkctrl = 0x4ae07890, + .cm_wkupaon_io_srcomp_clkctrl = 0x4ae07898, .prm_vc_val_bypass = 0x4ae07ba0, .prm_vc_cfg_i2c_mode = 0x4ae07bb4, .prm_vc_cfg_i2c_clk = 0x4ae07bb8, @@ -502,7 +504,7 @@ struct prcm_regs const omap5_es2_prcm = { .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8, .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec, .cm_coreaon_bandgap_clkctrl = 0x4a008648, - + .cm_coreaon_io_srcomp_clkctrl = 0x4a008650, /* cm2.core */ .cm_l3_1_clkstctrl = 0x4a008700, @@ -650,6 +652,7 @@ struct prcm_regs const omap5_es2_prcm = { .cm_wkup_rtc_clkctrl = 0x4ae07980, .cm_wkup_bandgap_clkctrl = 0x4ae07988, .cm_wkupaon_scrm_clkctrl = 0x4ae07990, + .cm_wkupaon_io_srcomp_clkctrl = 0x4ae07998, .prm_vc_val_bypass = 0x4ae07ca0, .prm_vc_cfg_i2c_mode = 0x4ae07cb4, .prm_vc_cfg_i2c_clk = 0x4ae07cb8, diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h index 829d10f..52299fa 100644 --- a/arch/arm/include/asm/arch-omap5/clocks.h +++ b/arch/arm/include/asm/arch-omap5/clocks.h @@ -186,6 +186,10 @@ #define OPTFCLKEN_SCRM_CORE_SHIFT 8 #define OPTFCLKEN_SCRM_CORE_MASK (1 << 8) +/* CM_COREAON_IO_SRCOMP_CLKCTRL */ +#define OPTFCLKEN_SRCOMP_FCLK_SHIFT 8 +#define OPTFCLKEN_SRCOMP_FCLK_MASK (1 << 8) + /* Clock frequencies */ #define OMAP_SYS_CLK_FREQ_38_4_MHZ 38400000 #define OMAP_SYS_CLK_IND_38_4_MHZ 6 diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index ba2775b..d29be93 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -229,7 +229,26 @@ struct s32ktimer { #define CH_FLAGS_CHFLASH (0x1 << 2) #define CH_FLAGS_CHMMCSD (0x1 << 3) +/* CONTROL_SRCOMP_XXX_SIDE */ +#define OVERRIDE_XS_SHIFT 30 +#define OVERRIDE_XS_MASK (1 << 30) +#define SRCODE_READ_XS_SHIFT 12 +#define SRCODE_READ_XS_MASK (0xff << 12) +#define PWRDWN_XS_SHIFT 11 +#define PWRDWN_XS_MASK (1 << 11) +#define DIVIDE_FACTOR_XS_SHIFT 4 +#define DIVIDE_FACTOR_XS_MASK (0x7f << 4) +#define MULTIPLY_FACTOR_XS_SHIFT 1 +#define MULTIPLY_FACTOR_XS_MASK (0x7 << 1) +#define SRCODE_OVERRIDE_SEL_XS_SHIFT 0 +#define SRCODE_OVERRIDE_SEL_XS_MASK (1 << 0) + #ifndef __ASSEMBLY__ +struct srcomp_params { + s8 divide_factor; + s8 multiply_factor; +}; + struct omap_boot_parameters { char *boot_message; unsigned int mem_boot_descriptor; diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index 201ed6f..b8d841d 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -59,6 +59,7 @@ int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); u32 warm_reset(void); void force_emif_self_refresh(void); void get_ioregs(const struct ctrl_ioregs **regs); +void srcomp_enable(void); /* * This is used to verify if the configuration header diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 8a886ec..0af0c33 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -153,6 +153,7 @@ struct prcm_regs { /* cm2.core */ u32 cm_coreaon_bandgap_clkctrl; + u32 cm_coreaon_io_srcomp_clkctrl; u32 cm_l3_1_clkstctrl; u32 cm_l3_1_dynamicdep; u32 cm_l3_1_l3_1_clkctrl; @@ -300,6 +301,7 @@ struct prcm_regs { u32 cm_wkup_rtc_clkctrl; u32 cm_wkup_bandgap_clkctrl; u32 cm_wkupaon_scrm_clkctrl; + u32 cm_wkupaon_io_srcomp_clkctrl; u32 prm_vc_val_bypass; u32 prm_vc_cfg_i2c_mode; u32 prm_vc_cfg_i2c_clk;