From patchwork Tue Jan 8 11:18:54 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: SRICHARAN R X-Patchwork-Id: 210341 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id D2B8B2C0084 for ; Tue, 8 Jan 2013 22:19:07 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6508E4A114; Tue, 8 Jan 2013 12:19:06 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id PvigD6rCO2gW; Tue, 8 Jan 2013 12:19:05 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 64F4D4A0F7; Tue, 8 Jan 2013 12:19:04 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 592B94A0F8 for ; Tue, 8 Jan 2013 12:19:02 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id RYI7CpXmeYRg for ; Tue, 8 Jan 2013 12:19:01 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from bear.ext.ti.com (bear.ext.ti.com [192.94.94.41]) by theia.denx.de (Postfix) with ESMTPS id 452874A0F5 for ; Tue, 8 Jan 2013 12:18:59 +0100 (CET) Received: from dbdp20.itg.ti.com ([172.24.170.38]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id r08BIujm011200 for ; Tue, 8 Jan 2013 05:18:57 -0600 Received: from DBDE70.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id r08BIuqw000688 for ; Tue, 8 Jan 2013 16:48:56 +0530 (IST) Received: from dbdp32.itg.ti.com (172.24.170.251) by dbde70.ent.ti.com (172.24.170.148) with Microsoft SMTP Server id 14.1.323.3; Tue, 8 Jan 2013 16:48:56 +0530 Received: from localhost.localdomain (smtpvbd.itg.ti.com [172.24.170.250]) by dbdp32.itg.ti.com (8.13.8/8.13.8) with ESMTP id r08BIu5T010324; Tue, 8 Jan 2013 16:48:56 +0530 From: R Sricharan To: , , Date: Tue, 8 Jan 2013 16:48:54 +0530 Message-ID: <1357643936-29365-1-git-send-email-r.sricharan@ti.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 Subject: [U-Boot] [RFC PATCH 1/2] ARM: cache: Introduce weak dram_bank_setup function X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Introduce a weak version of dram_bank_setup function to allow a platform specific redefinition. This is used in the subsequent patch to setup dram region without 'XN' attribute in order to enable the region under client permissions. Signed-off-by: R Sricharan Cc: Vincent Stehle Cc: Tom Rini --- arch/arm/include/asm/cache.h | 1 + arch/arm/lib/cache-cp15.c | 7 ++++++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index eef6a5a..93811d2 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -42,6 +42,7 @@ static inline void invalidate_l2_cache(void) void l2_cache_enable(void); void l2_cache_disable(void); +void dram_bank_mmu_setup(int bank); /* * The current upper bound for ARM L1 data cache line sizes is 64 bytes. We * use that value for aligning DMA buffers unless the board config has specified diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 6edf815..843078e 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -23,6 +23,8 @@ #include #include +#include +#include #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) @@ -77,7 +79,7 @@ void mmu_set_region_dcache_behaviour(u32 start, int size, mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]); } -static inline void dram_bank_mmu_setup(int bank) +void __dram_bank_mmu_setup(int bank) { bd_t *bd = gd->bd; int i; @@ -94,6 +96,9 @@ static inline void dram_bank_mmu_setup(int bank) } } +void dram_bank_mmu_setup(int bank) + __attribute__((weak, alias("__dram_bank_mmu_setup"))); + /* to activate the MMU we need to set up virtual memory: use 1M areas */ static inline void mmu_setup(void) {