From patchwork Mon Jan 7 14:44:39 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Vincent_Stehl=C3=A9?= X-Patchwork-Id: 209941 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 6CEBB2C007C for ; Tue, 8 Jan 2013 01:45:26 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1F0E04A0F3; Mon, 7 Jan 2013 15:45:24 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id CLuVdvKSHTYN; Mon, 7 Jan 2013 15:45:23 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5E3334A100; Mon, 7 Jan 2013 15:45:11 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 495484A0F1 for ; Mon, 7 Jan 2013 15:45:07 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id mpXs45tYXWUM for ; Mon, 7 Jan 2013 15:45:04 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from comal.ext.ti.com (comal.ext.ti.com [198.47.26.152]) by theia.denx.de (Postfix) with ESMTPS id 5F5224A0C0 for ; Mon, 7 Jan 2013 15:45:03 +0100 (CET) Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id r07Ej0k1009694; Mon, 7 Jan 2013 08:45:00 -0600 Received: from DLEE74.ent.ti.com (dlee74.ent.ti.com [157.170.170.8]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id r07Ej0oQ032164; Mon, 7 Jan 2013 08:45:00 -0600 Received: from dlelxv24.itg.ti.com (172.17.1.199) by DLEE74.ent.ti.com (157.170.170.8) with Microsoft SMTP Server id 14.1.323.3; Mon, 7 Jan 2013 08:44:59 -0600 Received: from svrhermes.tif.ti.com (svrhermes.tif.ti.com [137.167.130.169]) by dlelxv24.itg.ti.com (8.13.8/8.13.8) with ESMTP id r07EixXB024902; Mon, 7 Jan 2013 08:44:59 -0600 Received: from unb0919505.tif.ti.com (unb0919505.tif.ti.com [137.167.100.142]) by svrhermes.tif.ti.com (Postfix) with ESMTP id 23FB937011; Mon, 7 Jan 2013 15:44:59 +0100 (MET) Received: from vstehle by unb0919505.tif.ti.com with local (Exim 4.76) (envelope-from ) id 1TsDwg-0002e3-Jw; Mon, 07 Jan 2013 15:44:58 +0100 From: =?UTF-8?q?Vincent=20Stehl=C3=A9?= To: Date: Mon, 7 Jan 2013 15:44:39 +0100 Message-ID: <1357569880-10067-3-git-send-email-v-stehle@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1357569880-10067-1-git-send-email-v-stehle@ti.com> References: <92476020c6e1ef888207ca6f661c48068050efbf> <1357569880-10067-1-git-send-email-v-stehle@ti.com> MIME-Version: 1.0 Cc: Tom Rini Subject: [U-Boot] [PATCH v4 2/3] ARM: cache: introduce weak arm_setup_identity_mapping X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Separate the MMU identity mapping for ARM in a weak function, to allow redefinition with platform specific function. This is motivated by the need to unmap the region near address zero on HS OMAP devices, to avoid speculative accesses. Accessing this region causes security violations, which we want to avoid. Signed-off-by: Vincent Stehlé Cc: Tom Rini --- Changes for v4; - Use set_section_dcache() function - Remove page_table argument Changes for v3: - Add definition of __arm_setup_identity_mapping() into asm/cache.h - Fix comments style arch/arm/include/asm/cache.h | 1 + arch/arm/lib/cache-cp15.c | 22 +++++++++++++++++++--- 2 files changed, 20 insertions(+), 3 deletions(-) diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index 416d2c8..b898dc5 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -42,6 +42,7 @@ static inline void invalidate_l2_cache(void) void l2_cache_enable(void); void l2_cache_disable(void); void set_section_dcache(int section, enum dcache_option option); +void __arm_setup_identity_mapping(void); /* * The current upper bound for ARM L1 data cache line sizes is 64 bytes. We diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 6edf815..fa7b0c5 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -23,6 +23,8 @@ #include #include +#include +#include #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) @@ -34,6 +36,17 @@ void __arm_init_before_mmu(void) void arm_init_before_mmu(void) __attribute__((weak, alias("__arm_init_before_mmu"))); +void __arm_setup_identity_mapping(void) +{ + int i; + + /* Set up an identity-mapping for all 4GB, rw for everyone */ + for (i = 0; i < 4096; i++) + set_section_dcache(i, DCACHE_OFF); +} +__weak void arm_setup_identity_mapping(void) + __attribute__((alias("__arm_setup_identity_mapping"))); + static void cp_delay (void) { volatile int i; @@ -101,9 +114,12 @@ static inline void mmu_setup(void) u32 reg; arm_init_before_mmu(); - /* Set up an identity-mapping for all 4GB, rw for everyone */ - for (i = 0; i < 4096; i++) - set_section_dcache(i, DCACHE_OFF); + + /* + * Set up an identity-mapping. Default version maps all 4GB rw for + * everyone + */ + arm_setup_identity_mapping(); for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { dram_bank_mmu_setup(i);