From patchwork Sat Dec 22 00:16:38 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Warren X-Patchwork-Id: 207902 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 34FF82C0085 for ; Sat, 22 Dec 2012 11:23:26 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 88F754A0AE; Sat, 22 Dec 2012 01:23:24 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 457v5y7Jw5nV; Sat, 22 Dec 2012 01:23:24 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3EA854A09B; Sat, 22 Dec 2012 01:23:22 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CE7CF4A09B for ; Sat, 22 Dec 2012 01:23:16 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id IxzMBHJAEpqM for ; Sat, 22 Dec 2012 01:23:16 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pb0-f43.google.com (mail-pb0-f43.google.com [209.85.160.43]) by theia.denx.de (Postfix) with ESMTPS id 9BD574A099 for ; Sat, 22 Dec 2012 01:23:13 +0100 (CET) Received: by mail-pb0-f43.google.com with SMTP id um15so3021302pbc.16 for ; Fri, 21 Dec 2012 16:23:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-nvconfidentiality; bh=89kTrkL/1vOuuqA5khH2cDhrZcuOmUGylQEfYqBBbcc=; b=IMCnGtp7eUKVw+PDOMIgjsGqVIHi/Ac0GIE5FV70OocwM0oSsKvRYZrxKKy+IZETIi jYZcmpI2esGuVMJ5rkkkVTBTt+5wCZ6V9GsSzOMwXnnbt43DGJ4dv0cJGLiZuK9uZ+k0 8JTaDBeKKq3JYvYYBi7UkTv2g4PSpXUXD2ANWaMpWGTzPxTJdEIAueKuNYVwO7F9ShgS eiRX8cJLjho9DXCu2JaaxSE6wnQ84saEwKyJjFaoFdxqa3cF1x+cyIkbQhpu93c0bVJQ AeHO1GQKh2n6r/04RhwwfKbfSTiMK3gZEG0bfZFGN2NvzD2lfsfrUx5vkp95ERUGAgvK J8Iw== X-Received: by 10.68.245.67 with SMTP id xm3mr44081874pbc.152.1356135416864; Fri, 21 Dec 2012 16:16:56 -0800 (PST) Received: from localhost.localdomain (ip68-230-103-25.ph.ph.cox.net. [68.230.103.25]) by mx.google.com with ESMTPS id nw9sm7781466pbb.42.2012.12.21.16.16.54 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 21 Dec 2012 16:16:56 -0800 (PST) From: Tom Warren To: u-boot@lists.denx.de Date: Fri, 21 Dec 2012 17:16:38 -0700 Message-Id: <1356135399-28339-3-git-send-email-twarren@nvidia.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1356135399-28339-1-git-send-email-twarren@nvidia.com> References: <1356135399-28339-1-git-send-email-twarren@nvidia.com> X-NVConfidentiality: public Cc: swarren@nvidia.com, Tom Warren , twarren.nvidia@gmail.com Subject: [U-Boot] [PATCH 2/3] Tegra30: fdt: Update DT files with I2C info for T30/Cardhu X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Note that T30 does not have a separate/different DVC (power I2C) controller like T20 - all 5 I2C controllers are identical, but DVC_I2C is still used to designate the controller intended for power control (PWR_I2C in the schematics). On Cardhu, it's used to access the PMU and EEPROM, as well as the audio codec, temp sensor, and fuel gauge devices from the OS. Signed-off-by: Tom Warren --- arch/arm/dts/tegra30.dtsi | 61 +++++++++++++++++++++++++++++++++++ board/nvidia/dts/tegra30-cardhu.dts | 41 +++++++++++++++++++++++ 2 files changed, 102 insertions(+), 0 deletions(-) diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi index f568d44..664c397 100644 --- a/arch/arm/dts/tegra30.dtsi +++ b/arch/arm/dts/tegra30.dtsi @@ -2,4 +2,65 @@ / { compatible = "nvidia,tegra30"; + + tegra_car: clock@60006000 { + compatible = "nvidia,tegra30-car", "nvidia,tegra20-car"; + reg = <0x60006000 0x1000>; + #clock-cells = <1>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + osc: clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + }; + + i2c@7000c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000C000 0x100>; + /* PERIPH_ID_I2C1, CLK_M */ + clocks = <&tegra_car 12>; + }; + + i2c@7000c400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000C400 0x100>; + /* PERIPH_ID_I2C2, CLK_M */ + clocks = <&tegra_car 54>; + }; + + i2c@7000c500 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000C500 0x100>; + /* PERIPH_ID_I2C3, CLK_M */ + clocks = <&tegra_car 67>; + }; + + i2c@7000c700 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000C700 0x100>; + /* PERIPH_ID_I2C4, CLK_M */ + clocks = <&tegra_car 103>; + }; + + i2c@7000d000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; + reg = <0x7000D000 0x100>; + /* PERIPH_ID_I2C_DVC, CLK_M */ + clocks = <&tegra_car 47>; + }; }; diff --git a/board/nvidia/dts/tegra30-cardhu.dts b/board/nvidia/dts/tegra30-cardhu.dts index 2345766..4eddde6 100644 --- a/board/nvidia/dts/tegra30-cardhu.dts +++ b/board/nvidia/dts/tegra30-cardhu.dts @@ -6,8 +6,49 @@ model = "NVIDIA Cardhu"; compatible = "nvidia,cardhu", "nvidia,tegra30"; + aliases { + i2c0 = "/i2c@7000d000"; + i2c1 = "/i2c@7000c000"; + i2c2 = "/i2c@7000c400"; + i2c3 = "/i2c@7000c500"; + i2c4 = "/i2c@7000c700"; + }; + memory { device_type = "memory"; reg = <0x80000000 0x40000000>; }; + + clocks { + clk_32k: clk_32K { + clock-frequency = <32768>; + }; + osc { + clock-frequency = <12000000>; + }; + }; + + clock@60006000 { + clocks = <&clk_32k &osc>; + }; + + i2c@7000c000 { + clock-frequency = <100000>; + }; + + i2c@7000c400 { + clock-frequency = <100000>; + }; + + i2c@7000c500 { + clock-frequency = <100000>; + }; + + i2c@7000c700 { + clock-frequency = <100000>; + }; + + i2c@7000d000 { + clock-frequency = <100000>; + }; };