From patchwork Fri Nov 30 06:29:35 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajeshwari Birje X-Patchwork-Id: 202874 X-Patchwork-Delegate: promsoft@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 0FD6D2C0097 for ; Fri, 30 Nov 2012 17:23:32 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8557E4A046; Fri, 30 Nov 2012 07:23:31 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id XVTQRhI+Vis8; Fri, 30 Nov 2012 07:23:31 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D1EB94A030; Fri, 30 Nov 2012 07:23:26 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1911B4A030 for ; Fri, 30 Nov 2012 07:23:25 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id xWtK5IW2nvkX for ; Fri, 30 Nov 2012 07:23:23 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mailout2.samsung.com (mailout2.samsung.com [203.254.224.25]) by theia.denx.de (Postfix) with ESMTP id 1A4DF4A029 for ; Fri, 30 Nov 2012 07:23:21 +0100 (CET) Received: from epcpsbgm2.samsung.com (epcpsbgm2 [203.254.230.27]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MEA00G76F2GY3C0@mailout2.samsung.com> for u-boot@lists.denx.de; Fri, 30 Nov 2012 15:23:19 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.126]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 2D.78.12699.6D058B05; Fri, 30 Nov 2012 15:23:19 +0900 (KST) X-AuditID: cbfee61b-b7f616d00000319b-3e-50b850d61d65 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 6B.78.12699.6D058B05; Fri, 30 Nov 2012 15:23:18 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MEA00GZNF2NX3A0@mmp1.samsung.com> for u-boot@lists.denx.de; Fri, 30 Nov 2012 15:23:18 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Date: Fri, 30 Nov 2012 11:59:35 +0530 Message-id: <1354256975-24720-1-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrKLMWRmVeSWpSXmKPExsWyRsSkTvd6wI4Ag8PNjBZv93ayOzB6nL2z gzGAMYrLJiU1J7MstUjfLoEr4+iv3IKj3BWHnzazNDAe4Oxi5OSQEDCR+Du7jRnCFpO4cG89 WxcjF4eQwFJGidWrdrDAFH06up4FIrGIUeLvtw1QziomiaOrloG1swkYSWw9OY0RxBYRkJD4 1X+VEaSIWaCLUeLml+dgo4QF9CW6lk5gB7FZBFQlFu6YBNbMK+Ah8fPsFHaIdQoSx6Z+ZYWo EZD4NvkQUC8HUFxWYtMBZpCZEgJ72CQeLtwEdZ6kxMEVN1gmMAouYGRYxSiaWpBcUJyUnmuk V5yYW1yal66XnJ+7iREYVqf/PZPewbiqweIQowAHoxIPL8Oa7QFCrIllxZW5hxglOJiVRHj3 Ce4IEOJNSaysSi3Kjy8qzUktPsToA3TJRGYp0eR8YMjnlcQbGpuYmxqbWhoZmZma4hBWEudt 9kgJEBJITyxJzU5NLUgtghnHxMEp1cBoLveHyWq+WnLv1mM/GJNv876+kF621FCiWMfZ4aKu S8ibyaHnZN5OO+C+ru7Nawfpk28Eqo+t5bwk++jL9fMvZB/fnZMS/lAg8928wwpZzzTLbrNO mNM1ZZuf/Pk1W939flVWH7t1TbuunOPLfub8gmWpax+yTkm8yymqueR5zk/lqGNmuZ86lViK MxINtZiLihMBYgQnelgCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrCLMWRmVeSWpSXmKPExsVy+t9jAd1rATsCDA4061m83dvJ7sDocfbO DsYAxqgGRpuM1MSU1CKF1Lzk/JTMvHRbJe/geOd4UzMDQ11DSwtzJYW8xNxUWyUXnwBdt8wc oLFKCmWJOaVAoYDE4mIlfTtME0JD3HQtYBojdH1DguB6jAzQQMIaxoyjv3ILjnJXHH7azNLA eICzi5GTQ0LAROLT0fUsELaYxIV769m6GLk4hAQWMUr8/baBBcJZxSRxdNUyZpAqNgEjia0n pzGC2CICEhK/+q8yghQxC3QxStz88hxslLCAvkTX0gnsIDaLgKrEwh2TwJp5BTwkfp6dwg6x TkHi2NSvrBMYuRcwMqxiFE0tSC4oTkrPNdIrTswtLs1L10vOz93ECA7aZ9I7GFc1WBxiFOBg VOLhZVizPUCINbGsuDL3EKMEB7OSCO8+wR0BQrwpiZVVqUX58UWlOanFhxh9gLZPZJYSTc4H RlReSbyhsYm5qbGppYmFiZklDmElcd5mj5QAIYH0xJLU7NTUgtQimHFMHJxSDYwep6LP3nhm 4Mkz8YX3s9zjUyuy14sklN3u3SC7dOmjltvLAop+Fu04HDv9wQmvF4dnf98c9OhJzUKTPYt+ yQSleOv42f56va9vrSrrJatFrk98t2al9b+r2fB0kkWJ2uuqFfMT953a/m7auYbqGNGZQXv2 l1Z1sOX/u2QY9bilVLWo4J/IPrEuJZbijERDLeai4kQArO4M2IcCAAA= X-CFilter-Loop: Reflected Cc: kmpark@infradead.org, patches@linaro.org Subject: [U-Boot] [PATCH] EXYNOS5: Add L2 Cache Support. X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This patch set adds L2 Cache Support to EXYNOS. Signed-off-by: Arun Mankuzhi Signed-off-by: Rajeshwari Shinde Acked-by: Simon Glass --- arch/arm/cpu/armv7/exynos/soc.c | 37 +++++++++++++++++++++++++++++++++++++ 1 files changed, 37 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/soc.c b/arch/arm/cpu/armv7/exynos/soc.c index ab65b8d..676a388 100644 --- a/arch/arm/cpu/armv7/exynos/soc.c +++ b/arch/arm/cpu/armv7/exynos/soc.c @@ -23,6 +23,14 @@ #include #include +#include + +enum l2_cache_params { + CACHE_TAG_RAM_SETUP = (1<<9), + CACHE_DATA_RAM_SETUP = (1<<5), + CACHE_TAG_RAM_LATENCY = (2<<6), + CACHE_DATA_RAM_LATENCY = (2<<0) +}; void reset_cpu(ulong addr) { @@ -36,3 +44,32 @@ void enable_caches(void) dcache_enable(); } #endif + +#ifndef CONFIG_SYS_L2CACHE_OFF +/* + * Set L2 cache parameters + */ +static void exynos5_set_l2cache_params(void) +{ + unsigned int val = 0; + + asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r"(val)); + + val |= CACHE_TAG_RAM_SETUP | + CACHE_DATA_RAM_SETUP | + CACHE_TAG_RAM_LATENCY | + CACHE_DATA_RAM_LATENCY; + + asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val)); +} + +/* + * Sets L2 cache related parameters before enabling data cache + */ +void v7_outer_cache_enable(void) +{ + if (cpu_is_exynos5()) + exynos5_set_l2cache_params(); +} +#endif +