From patchwork Thu Nov 1 23:42:02 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 196420 X-Patchwork-Delegate: albert.aribaud@free.fr Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id A2B802C0343 for ; Fri, 2 Nov 2012 10:44:19 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 92C5E4A72A; Fri, 2 Nov 2012 00:43:57 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id u3G-3LD6ndT3; Fri, 2 Nov 2012 00:43:57 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E38E34A6C0; Fri, 2 Nov 2012 00:43:27 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 32F754A6A5 for ; Fri, 2 Nov 2012 00:43:23 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id zd8sPS3VhDba for ; Fri, 2 Nov 2012 00:43:22 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-lb0-f202.google.com (mail-lb0-f202.google.com [209.85.217.202]) by theia.denx.de (Postfix) with ESMTPS id 85A054A696 for ; Fri, 2 Nov 2012 00:43:17 +0100 (CET) Received: by mail-lb0-f202.google.com with SMTP id l12so191461lbo.3 for ; Thu, 01 Nov 2012 16:43:17 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=Mo8e89kys/6DenjrJKOk1QH0HDWVbu99vxt49nz3APA=; b=nmjeJPprONh4iCbde5T48pTUY4rfPJc6IAS3DidXynRf21YLa96z6PWg9Ly4FX5vDT RNA1FyUvH46SrrZH6uHVxiGrSphrkZpbzeM5OMtIBTB3fv2TjRqLO9WyJjBM9sMZpZ5H xa/iS8RkVXnVOffHaRzgs6QMus9hqNrP20dA/Ev9YZIa5gOG+GhxY6VEMSHzfo0izsqJ rlB0e8MWzUJlcqYw917ZoY5ssDJGusJOPFmRkOjnB4BFkEkE1YBCOlq7P4It4Oz1/8cU NonYfqDtQFoIpYeNFdn7iR7Dug9a4k2le+V7Ghfqbs3qpmYpgrVvzcE92RmSk6o+wrGw qf3g== Received: by 10.14.216.7 with SMTP id f7mr90380eep.4.1351813394956; Thu, 01 Nov 2012 16:43:14 -0700 (PDT) Received: from hpza9.eem.corp.google.com ([74.125.121.33]) by gmr-mx.google.com with ESMTPS id u8si1013782een.1.2012.11.01.16.43.14 (version=TLSv1/SSLv3 cipher=AES128-SHA); Thu, 01 Nov 2012 16:43:14 -0700 (PDT) Received: from kaka.mtv.corp.google.com (kaka.mtv.corp.google.com [172.22.73.79]) by hpza9.eem.corp.google.com (Postfix) with ESMTP id 95A845C0050; Thu, 1 Nov 2012 16:43:14 -0700 (PDT) Received: by kaka.mtv.corp.google.com (Postfix, from userid 121222) id F35BB16091E; Thu, 1 Nov 2012 16:43:13 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Date: Thu, 1 Nov 2012 16:42:02 -0700 Message-Id: <1351813330-23741-2-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 1.7.7.3 In-Reply-To: <1351813330-23741-1-git-send-email-sjg@chromium.org> References: <1351813330-23741-1-git-send-email-sjg@chromium.org> X-Gm-Message-State: ALoCoQmCJRaN+5JUAr7I2m+3GDtrOjkce7wB4LOniADga+9cfag+rB2A/FnJb5UuwuoXmaVvgIIFejzObQxtQ6TtVeJQv2lwd1W7cLxpZjcDkBvHg6E1xrozOCOqlfFblI1bw7rPRrViRFgwMVnnsWaIpg3U9TynRjy3u5LYFMUsfPVCGsPik1N/Cz1HfimoLDVYZy8XChop Cc: Arun Mankuzhi Subject: [U-Boot] [PATCH 02/10] arm: move flush_dcache_all() to just before disable cache X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Arun Mankuzhi In Cortex-A15 architecture, when we run cache invalidate the cache clean operation executes automatically. So if there are any dirty cache lines before disabling the L2 cache these will be synchronized with the main memory when invalidate_dcache_all() runs in the last part of U-boot The two functions after flush_dcache_all is using the stack. So this data will be on the cache. After disable when invalidate is called the data will be flushed from cache to memory. This corrupts the stack in invalida_dcache_all. So this change is required to avoid the u-boot hang. So flush has to be done just before clearing CR_C bit Signed-off-by: Arun Mankuzhi Signed-off-by: Simon Glass --- arch/arm/lib/cache-cp15.c | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-) diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 8f8385d..03b9c80 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -134,8 +134,11 @@ static void cache_disable(uint32_t cache_bit) return; /* if disabling data cache, disable mmu too */ cache_bit |= CR_M; - flush_dcache_all(); } + reg = get_cr(); + cp_delay(); + if (cache_bit == (CR_C | CR_M)) + flush_dcache_all(); set_cr(reg & ~cache_bit); } #endif