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Mon, 22 Oct 2012 20:57:40 +0900 (KST) Received: from hatim-linux.sisodomain.com ([107.108.73.95]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MCA006A7MH2ZQ10@mmp1.samsung.com> for u-boot@lists.denx.de; Mon, 22 Oct 2012 20:57:40 +0900 (KST) From: Hatim Ali To: u-boot@lists.denx.de Date: Mon, 22 Oct 2012 17:22:04 +0530 Message-id: <1350906729-23749-2-git-send-email-hatim.rv@samsung.com> X-Mailer: git-send-email 1.7.2.3 In-reply-to: <1350906729-23749-1-git-send-email-hatim.rv@samsung.com> References: <1350906729-23749-1-git-send-email-hatim.rv@samsung.com> DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrJLMWRmVeSWpSXmKPExsWyRsSkTnerSWuAwbJLXBZv93ayOzB6nL2z gzGAMYrLJiU1J7MstUjfLoErY8quaewFf8QqpnU+ZWtgvCXUxcjBISFgIvHhgEcXIyeQKSZx 4d56ti5GLg4hgaWMEg3LZ7PD1Bzvt4GIL2KUmN+6B6poCZNEz4M2ZpBuNgE1ifWvO9lAbBEB CYlf/VcZQWxmARuJJT33wGxhAWuJSatugNWzCKhKXN/Yxg5i8wq4SDS9amWEuEJB4tWNtWBx TgFXifv9HawgRwgB1czvVYRoFZD4NvkQC8RtshKbDjBDdF5mk3hxDsqWlDi44gbLBEbhBYwM qxhFUwuSC4qT0nON9IoTc4tL89L1kvNzNzECw+/0v2fSOxhXNVgcYhTgYFTi4V3wuSVAiDWx rLgy9xCjBAezkgjvFbHWACHelMTKqtSi/Pii0pzU4kOMPkCHTGSWEk3OB8ZGXkm8obGJuamx qaWRkZmpKQ5hJXHeZo+UACGB9MSS1OzU1ILUIphxTBycUg2MKneMJcQY7s7yuGlwTz11hvRm iTD/3dHhKhkeF5i89H4vi/PQcJv1+HPehVtrbrN0CpbUCn2xlGr8tstsUdHyG3vSZkqldS9a lBc22znv3Fe71RIdF8M/9jj8Xdd3sL9j6okj+yROn9Hs+uPuWejIt2u9YXzGyXb9I5ZX/jLx ZYrv0NW8ETxViaU4I9FQi7moOBEA9nFFB2wCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupikeLIzCtJLcpLzFFi42I5/e+xgO4Wk9YAg3UrLS3e7u1kd2D0OHtn B2MAY1QDo01GamJKapFCal5yfkpmXrqtkndwvHO8qZmBoa6hpYW5kkJeYm6qrZKLT4CuW2YO 0FglhbLEnFKgUEBicbGSvh2mCaEhbroWMI0Rur4hQXA9RgZoIGENY8aUXdPYC/6IVUzrfMrW wHhLqIuRg0NCwETieL9NFyMnkCkmceHeerYuRi4OIYFFjBLzW/dAOUuYJHoetDGDVLEJqEms f93JBmKLCEhI/Oq/yghiMwvYSCzpuQdmCwtYS0xadQOsnkVAVeL6xjZ2EJtXwEWi6VUrI8Q2 BYlXN9aCxTkFXCXu93ewghwkBFQzv1dxAiPvAkaGVYyiqQXJBcVJ6blGesWJucWleel6yfm5 mxjBAf5MegfjqgaLQ4wCHIxKPLwLPrcECLEmlhVX5h5ilOBgVhLhvSLWGiDEm5JYWZValB9f VJqTWnyI0QfoqInMUqLJ+cDoyyuJNzQ2MTc1NrU0sTAxs8QhrCTO2+yREiAkkJ5YkpqdmlqQ WgQzjomDU6qBsSLM/s1h04haAb8IntmiLqEaYvqB3LvEeEzjryg4qM8L57j7fNfBxIl33/2J VP8ktoylOORuw/LF5/5lWmsmKVmkvZl/lveoeJ7zuVTpouq12Rmfpr0RWv78mZpPutnmlXNz dTYxHfl37/JXB59NPBeMW2761eb223ZE/418K1G3Me32jk+TlFiKMxINtZiLihMBPxhcxZ0C AAA= X-CFilter-Loop: Reflected Cc: patches@linaro.org Subject: [U-Boot] [PATCH 1/6 V7] EXYNOS5: Add pinmux support for SPI X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Rajeshwari Shinde This patch adds pinmux support for SPI channels Signed-off-by: Rajeshwari Shinde Signed-off-by: Hatim Ali Acked-by: Simon Glass --- Changes since v4: Fixed minor nits suggested by Simon Glass Changes since v5: No change Changes since v6: Incorporated review comments by Simon Glass & Minkyu Kang diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 5796d56..3ecbf7d 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -112,6 +112,7 @@ static int exynos5_mmc_config(int peripheral, int flags) s5p_gpio_set_pull(bank, i, GPIO_PULL_UP); s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); } + return 0; } @@ -230,6 +231,49 @@ static void exynos5_i2c_config(int peripheral, int flags) } } +void exynos5_spi_config(int peripheral) +{ + int cfg = 0, pin = 0, i; + struct s5p_gpio_bank *bank = NULL; + struct exynos5_gpio_part1 *gpio1 = + (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); + struct exynos5_gpio_part2 *gpio2 = + (struct exynos5_gpio_part2 *) samsung_get_base_gpio_part2(); + + switch (peripheral) { + case PERIPH_ID_SPI0: + bank = &gpio1->a2; + cfg = GPIO_FUNC(0x2); + pin = 0; + break; + case PERIPH_ID_SPI1: + bank = &gpio1->a2; + cfg = GPIO_FUNC(0x2); + pin = 4; + break; + case PERIPH_ID_SPI2: + bank = &gpio1->b1; + cfg = GPIO_FUNC(0x5); + pin = 1; + break; + case PERIPH_ID_SPI3: + bank = &gpio2->f1; + cfg = GPIO_FUNC(0x2); + pin = 0; + break; + case PERIPH_ID_SPI4: + for (i = 0; i < 2; i++) { + s5p_gpio_cfg_pin(&gpio2->f0, i + 2, GPIO_FUNC(0x4)); + s5p_gpio_cfg_pin(&gpio2->e0, i + 4, GPIO_FUNC(0x4)); + } + break; + } + if (peripheral != PERIPH_ID_SPI4) { + for (i = pin; i < pin + 4; i++) + s5p_gpio_cfg_pin(bank, i, cfg); + } +} + static int exynos5_pinmux_config(int peripheral, int flags) { switch (peripheral) { @@ -257,6 +301,13 @@ static int exynos5_pinmux_config(int peripheral, int flags) case PERIPH_ID_I2C7: exynos5_i2c_config(peripheral, flags); break; + case PERIPH_ID_SPI0: + case PERIPH_ID_SPI1: + case PERIPH_ID_SPI2: + case PERIPH_ID_SPI3: + case PERIPH_ID_SPI4: + exynos5_spi_config(peripheral); + break; default: debug("%s: invalid peripheral %d", __func__, peripheral); return -1; diff --git a/arch/arm/include/asm/arch-exynos/periph.h b/arch/arm/include/asm/arch-exynos/periph.h index 082611c..4054fb6 100644 --- a/arch/arm/include/asm/arch-exynos/periph.h +++ b/arch/arm/include/asm/arch-exynos/periph.h @@ -44,6 +44,11 @@ enum periph_id { PERIPH_ID_SDMMC3, PERIPH_ID_SDMMC4, PERIPH_ID_SROMC, + PERIPH_ID_SPI0, + PERIPH_ID_SPI1, + PERIPH_ID_SPI2, + PERIPH_ID_SPI3, + PERIPH_ID_SPI4, PERIPH_ID_UART0, PERIPH_ID_UART1, PERIPH_ID_UART2,