From patchwork Mon Oct 15 23:32:09 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Estevam X-Patchwork-Id: 191680 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 867772C00A7 for ; Tue, 16 Oct 2012 10:32:55 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id EE99F4A11E; Tue, 16 Oct 2012 01:32:53 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id AvjrlBbQZR-d; Tue, 16 Oct 2012 01:32:53 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 786CD4A13D; Tue, 16 Oct 2012 01:32:44 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 655384A118 for ; Tue, 16 Oct 2012 01:32:42 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id y78-IF0UM0ym for ; Tue, 16 Oct 2012 01:32:40 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-gh0-f172.google.com (mail-gh0-f172.google.com [209.85.160.172]) by theia.denx.de (Postfix) with ESMTPS id 831E44A136 for ; Tue, 16 Oct 2012 01:32:35 +0200 (CEST) Received: by mail-gh0-f172.google.com with SMTP id g10so1457432ghb.3 for ; Mon, 15 Oct 2012 16:32:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=QJPdVypaoKC0SP90peHGhy9RpSt+/ubPdwwIgRTFeiU=; b=JZYdPuZcSqyJdfLvO2jstKh3jPspp+O0JJBEJJD/Kcasg6cJs4B3rNW0yYOwp7FN9Z TfBylD6nAbWcFITH9k8BvWhosqqZ6qq3otkF862DWBdNJi8oZguhd+o5zfWyhxJa5gFO /VI6bqgwjtQgaL/DAZza2eoj+Gd8mtanVMdz2YJdAWHachWaGUvpDWOi6DTy5H/WIilQ ZanbeVCoxXKKUuWsYhx6BeTgnd4I/o8+FM0tQXg2YOVG9rHWsPWUmg/MN6vWHh9zySTC 2URim/EmYUH0nb7Cr1i5t+Mu3zWlScfpxjJZrU5t8hYxPSKTrcvRkv0EzAPg8htINnli q+Aw== Received: by 10.236.155.71 with SMTP id i47mr12300466yhk.72.1350343954409; Mon, 15 Oct 2012 16:32:34 -0700 (PDT) Received: from fabio-Latitude-E6410.cps.virtua.com.br ([201.82.136.72]) by mx.google.com with ESMTPS id m3sm1669295ank.22.2012.10.15.16.32.31 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 15 Oct 2012 16:32:34 -0700 (PDT) From: Fabio Estevam To: sbabic@denx.de Date: Mon, 15 Oct 2012 20:32:09 -0300 Message-Id: <1350343930-15648-4-git-send-email-festevam@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1350343930-15648-1-git-send-email-festevam@gmail.com> References: <1350343930-15648-1-git-send-email-festevam@gmail.com> Cc: Fabio Estevam , u-boot@lists.denx.de Subject: [U-Boot] [PATCH v2 4/5] pmic: Add support for mc34704 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Fabio Estevam Add the register layout for the MC34704 PMIC from Freescale. Signed-off-by: Fabio Estevam --- Changes since v2: - No changes. Newly introduced in this series include/mc34704.h | 49 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 include/mc34704.h diff --git a/include/mc34704.h b/include/mc34704.h new file mode 100644 index 0000000..a0bb91a --- /dev/null +++ b/include/mc34704.h @@ -0,0 +1,49 @@ +/* + * (C) Copyright 2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + */ + +#ifndef __MC34704_H__ +#define __MC34704_H__ + +enum { + MC34704_RESERVED0_REG = 0, /* 0x00 */ + MC34704_GENERAL1_REG, /* 0x01 */ + MC34704_GENERAL2_REG, /* 0x02 */ + MC34704_GENERAL3_REG, /* 0x03 */ + MC34704_RESERVED4_REG, /* 0x04 */ + MC34704_VGSET2_REG, /* 0x05 */ + MC34704_REG2SET1_REG, /* 0x06 */ + MC34704_REG2SET2_REG, /* 0x07 */ + MC34704_REG3SET1_REG, /* 0x08 */ + MC34704_REG3SET2_REG, /* 0x09 */ + MC34704_REG4SET1_REG, /* 0x0a */ + MC34704_REG4SET2_REG, /* 0x0b */ + MC34704_REG5SET1_REG, /* 0x0c */ + MC34704_REG5SET2_REG, /* 0x0d */ + MC34704_REG5SET3_REG, /* 0x0e */ + MC34704_RESERVEDF_REG, /* 0x0f */ + MC34704_RESERVED10_REG, /* 0x10 */ + MC34704_RESERVED11_REG, /* 0x11 */ + MC34704_RESERVED12_REG, /* 0x12 */ + MC34704_FSW2SET_REG, /* 0x13 */ + MC34704_RESERVED14_REG, /* 0x14 */ + MC34704_REG8SET1_REG, /* 0x15 */ + MC34704_REG8SET2_REG, /* 0x16 */ + MC34704_REG8SET3_REG, /* 0x17 */ + MC34704_FAULTS_REG, /* 0x18 */ + MC34704_I2CSET1, /* 0x19 */ + MC34704_NUM_OF_REGS, +}; + +/* GENERAL2 register fields */ +#define ONOFFE (1 << 0) +#define ONOFFD (1 << 1) +#define ALLOFF (1 << 4) + +#endif /* __MC34704_H__ */