From patchwork Mon Aug 20 14:22:29 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhi-zhou Zhang X-Patchwork-Id: 178833 X-Patchwork-Delegate: daniel.schwierzeck@googlemail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 11E9B2C00B2 for ; Tue, 21 Aug 2012 00:25:08 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 05B2228588; Mon, 20 Aug 2012 16:24:33 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 3BRUss7ZdzWk; Mon, 20 Aug 2012 16:24:32 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id F29B728561; Mon, 20 Aug 2012 16:24:12 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 627D4284C8 for ; Mon, 20 Aug 2012 16:24:08 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id OYGQsH1FijKC for ; Mon, 20 Aug 2012 16:24:08 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pz0-f44.google.com (mail-pz0-f44.google.com [209.85.210.44]) by theia.denx.de (Postfix) with ESMTPS id 3FADF2852C for ; Mon, 20 Aug 2012 16:23:57 +0200 (CEST) Received: by mail-pz0-f44.google.com with SMTP id r19so2745408dak.3 for ; Mon, 20 Aug 2012 07:23:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=N7lWAThRsbaYklwWyWA/kWrYaLlpVpCITaaHc1FeiXs=; b=oVHibPPuHgBEtrlklmq3JXPyq1XJkJWaht3RAjCa1vE7PasxLzisnCK9fs+9VDpl9t E7LiDsV49omrQTrSBMv+OGlhtusByTTTz8jRXb4q1s/Fch+M9MBGABnbnijiGgZKWs5H 6wJJ52mTOupAGt1L1ytOzuVY3BF6ObtQY/TC4xBPWCOAGBWT7Cn34L6vk98wnC96MH23 9m6Bc4qZdSy9B8a93yK5Jl2PfnTKZpbF5j5oMFqSxrliTm8/v/gBgzA8kGiN488u95xy WOdQXKAa3oPAojzBaRaB6HP5DSrbOjrW21ULNb01leEC1gOfroRCtxxwnD5QSaYwx4af GSQQ== Received: by 10.68.136.137 with SMTP id qa9mr34611086pbb.140.1345472637790; Mon, 20 Aug 2012 07:23:57 -0700 (PDT) Received: from localhost.localdomain ([124.165.216.64]) by mx.google.com with ESMTPS id ox5sm11174086pbc.75.2012.08.20.07.23.53 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 20 Aug 2012 07:23:57 -0700 (PDT) From: Zhizhou Zhang To: u-boot@lists.denx.de Date: Mon, 20 Aug 2012 22:22:29 +0800 Message-Id: <1345472551-1546-8-git-send-email-etou.zh@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1345472551-1546-1-git-send-email-etou.zh@gmail.com> References: <1345472551-1546-1-git-send-email-etou.zh@gmail.com> Subject: [U-Boot] [Patch V3 2/4] [MIPS] add mips64 support in mips head files X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de The most important difference between mips32 and mips64 is the address space. changes in addrspace.h and io.h are for this sake. And this patch add cache discribe struct in cache.h, and make compatible to mips64 of some types in posix_types.h. Signed-off-by: Zhizhou Zhang --- arch/mips/include/asm/addrspace.h | 2 +- arch/mips/include/asm/cache.h | 21 +++++++++++++++++++++ arch/mips/include/asm/io.h | 18 +++++++++++++++++- arch/mips/include/asm/posix_types.h | 12 +++++++++--- 4 files changed, 48 insertions(+), 5 deletions(-) diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h index 3a1e6d6..b768bb5 100644 --- a/arch/mips/include/asm/addrspace.h +++ b/arch/mips/include/asm/addrspace.h @@ -136,7 +136,7 @@ cannot access physical memory directly from core */ #define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000) #else /* !CONFIG_SOC_AU1X00 */ -#define UNCACHED_SDRAM(a) KSEG1ADDR(a) +#define UNCACHED_SDRAM(a) CKSEG1ADDR(a) #endif /* CONFIG_SOC_AU1X00 */ #endif /* __ASSEMBLY__ */ diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h index 5406d5d..e41b9b4 100644 --- a/arch/mips/include/asm/cache.h +++ b/arch/mips/include/asm/cache.h @@ -33,4 +33,25 @@ #define ARCH_DMA_MINALIGN 128 #endif +/* + * Descriptor for a cache + */ +struct cache_desc { + unsigned int size; /* total size */ + unsigned int waysize; /* Bytes per way */ + unsigned short sets; /* Number of lines per set */ + unsigned char ways; /* Number of ways */ + unsigned char linesz; /* Size of line in bytes */ +}; + +#define cache_op(op,addr) \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noreorder \n" \ + " .set mips64\n\t \n" \ + " cache %0, %1 \n" \ + " .set pop \n" \ + : \ + : "i" (op), "R" (*(unsigned char *)(addr))) + #endif /* __MIPS_CACHE_H__ */ diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index 025012a..1b82c61 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -120,12 +120,20 @@ static inline void set_io_port_base(unsigned long base) */ extern inline phys_addr_t virt_to_phys(volatile void * address) { +#ifndef CONFIG_64BIT return CPHYSADDR(address); +#else + return XPHYSADDR(address); +#endif } extern inline void * phys_to_virt(unsigned long address) { - return (void *)KSEG0ADDR(address); +#ifndef CONFIG_64BIT + return (void *)KSEG0ADDR(address); +#else + return (void *)CKSEG0ADDR(address); +#endif } /* @@ -133,12 +141,20 @@ extern inline void * phys_to_virt(unsigned long address) */ extern inline unsigned long virt_to_bus(volatile void * address) { +#ifndef CONFIG_64BIT return CPHYSADDR(address); +#else + return XPHYSADDR(address); +#endif } extern inline void * bus_to_virt(unsigned long address) { +#ifndef CONFIG_64BIT return (void *)KSEG0ADDR(address); +#else + return (void *)CKSEG0ADDR(address); +#endif } /* diff --git a/arch/mips/include/asm/posix_types.h b/arch/mips/include/asm/posix_types.h index 879aae2..0da1dde 100644 --- a/arch/mips/include/asm/posix_types.h +++ b/arch/mips/include/asm/posix_types.h @@ -24,9 +24,15 @@ typedef int __kernel_pid_t; typedef int __kernel_ipc_pid_t; typedef int __kernel_uid_t; typedef int __kernel_gid_t; -typedef unsigned int __kernel_size_t; -typedef int __kernel_ssize_t; -typedef int __kernel_ptrdiff_t; +#ifndef CONFIG_MIPS64 + typedef unsigned int __kernel_size_t; + typedef int __kernel_ssize_t; + typedef int __kernel_ptrdiff_t; +#else +typedef unsigned long __kernel_size_t; +typedef long __kernel_ssize_t; +typedef long __kernel_ptrdiff_t; +#endif typedef long __kernel_time_t; typedef long __kernel_suseconds_t; typedef long __kernel_clock_t;