From patchwork Wed Aug 1 09:33:26 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajeshwari Birje X-Patchwork-Id: 174418 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 899EF2C009B for ; Wed, 1 Aug 2012 19:27:50 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 13AA2280C5; Wed, 1 Aug 2012 11:27:42 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 9P5lL74uMKOL; Wed, 1 Aug 2012 11:27:41 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 92D81280C6; Wed, 1 Aug 2012 11:27:26 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CFCA6280AD for ; Wed, 1 Aug 2012 11:27:21 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id tOmly07721d8 for ; Wed, 1 Aug 2012 11:27:20 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mailout4.samsung.com (mailout4.samsung.com [203.254.224.34]) by theia.denx.de (Postfix) with ESMTP id 55973280AF for ; Wed, 1 Aug 2012 11:27:20 +0200 (CEST) Received: from epcpsbgm2.samsung.com (mailout4.samsung.com [203.254.224.34]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M82004ZRKX8KJK0@mailout4.samsung.com> for u-boot@lists.denx.de; Wed, 01 Aug 2012 18:27:16 +0900 (KST) X-AuditID: cbfee61b-b7f566d000005c8a-dd-5018f673be15 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 3E.D2.23690.376F8105; Wed, 01 Aug 2012 18:27:15 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M820029AKX8FS00@mmp2.samsung.com> for u-boot@lists.denx.de; Wed, 01 Aug 2012 18:27:15 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Date: Wed, 01 Aug 2012 15:03:26 +0530 Message-id: <1343813612-1587-2-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1343813612-1587-1-git-send-email-rajeshwari.s@samsung.com> References: <1343813612-1587-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrAJMWRmVeSWpSXmKPExsVy+t9jQd3ibxIBBq2nrSze7u1kd2D0OHtn B2MAYxSXTUpqTmZZapG+XQJXxqRHj1kL7olWdP5oZGlgPCbYxcjJISFgIrGpZS8jhC0mceHe erYuRi4OIYHpjBKP5m5iBUkICaxikth3IRjEZhMwkth6chpYg4iAhMSv/qtANgcHs0CpxJSJ eSBhYQFribU7jrGA2CwCqhJt878ygdi8Au4SDb9XsEDsUpA4NvUrK0grp4CHxPedbBCb3CVu vd3FOoGRdwEjwypG0dSC5ILipPRcI73ixNzi0rx0veT83E2MYH8/k97BuKrB4hCjAAejEg/v CzOJACHWxLLiytxDjBIczEoivAU3gUK8KYmVValF+fFFpTmpxYcYpTlYlMR5Tby/+gsJpCeW pGanphakFsFkmTg4pRoYCy4bdtisnHRCL1bHZO/L7xovbO9pzF7u9JwjRP5s1Y3Ayw/vZh7r PKRTKdl3zCPR2N52Qf7R6tblqv7r1q/TUWu6UsWbsWT/2hWfe/OPm9h/aemut5t5KOuu9pT/ Pg3ve6ce2r5XW+jj6pub7fV27F1Yf90n6OoSr793Sl12F4Rqck15UBP7WomlOCPRUIu5qDgR ADAvU6nzAQAA X-TM-AS-MML: No Cc: alim.akhtar@samsung.com, patches@linaro.org Subject: [U-Boot] [PATCH 1/7 V3] EXYNOS5: Add pinmux support for SPI X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This patch adds pinmux support for SPI channels Signed-off-by: Rajeshwari Shinde --- Changes in V2: - None. Changes in V3: - Removed the slave flag for SPI. arch/arm/cpu/armv7/exynos/pinmux.c | 51 ++++++++++++++++++++++++++++- arch/arm/include/asm/arch-exynos/periph.h | 5 +++ 2 files changed, 55 insertions(+), 1 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 7776add..13f75e0 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -230,6 +230,49 @@ static void exynos5_i2c_config(int peripheral, int flags) } } +void exynos5_spi_config(int peripheral) +{ + int cfg = 0, pin = 0, i; + struct s5p_gpio_bank *bank = NULL; + struct exynos5_gpio_part1 *gpio1 = + (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); + struct exynos5_gpio_part2 *gpio2 = + (struct exynos5_gpio_part2 *) samsung_get_base_gpio_part2(); + + switch (peripheral) { + case PERIPH_ID_SPI0: + bank = &gpio1->a2; + cfg = GPIO_FUNC(0x2); + pin = 0; + break; + case PERIPH_ID_SPI1: + bank = &gpio1->a2; + cfg = GPIO_FUNC(0x2); + pin = 4; + break; + case PERIPH_ID_SPI2: + bank = &gpio1->b1; + cfg = GPIO_FUNC(0x5); + pin = 1; + break; + case PERIPH_ID_SPI3: + bank = &gpio2->f1; + cfg = GPIO_FUNC(0x2); + pin = 0; + break; + case PERIPH_ID_SPI4: + for (i = 2; i < 4; i++) + s5p_gpio_cfg_pin(&gpio2->f0, i, GPIO_FUNC(0x4)); + for (i = 4; i < 6; i++) + s5p_gpio_cfg_pin(&gpio2->e0, i, GPIO_FUNC(0x4)); + break; + } + if (peripheral != PERIPH_ID_SPI4) { + for (i = pin; i < pin + 4; i++) + s5p_gpio_cfg_pin(bank, i, cfg); + } +} + static int exynos5_pinmux_config(int peripheral, int flags) { switch (peripheral) { @@ -257,11 +300,17 @@ static int exynos5_pinmux_config(int peripheral, int flags) case PERIPH_ID_I2C7: exynos5_i2c_config(peripheral, flags); break; + case PERIPH_ID_SPI0: + case PERIPH_ID_SPI1: + case PERIPH_ID_SPI2: + case PERIPH_ID_SPI3: + case PERIPH_ID_SPI4: + exynos5_spi_config(peripheral); + break; default: debug("%s: invalid peripheral %d", __func__, peripheral); return -1; } - return 0; } diff --git a/arch/arm/include/asm/arch-exynos/periph.h b/arch/arm/include/asm/arch-exynos/periph.h index b861d7d..dafc3f3 100644 --- a/arch/arm/include/asm/arch-exynos/periph.h +++ b/arch/arm/include/asm/arch-exynos/periph.h @@ -43,6 +43,11 @@ enum periph_id { PERIPH_ID_SDMMC2, PERIPH_ID_SDMMC3, PERIPH_ID_SROMC, + PERIPH_ID_SPI0, + PERIPH_ID_SPI1, + PERIPH_ID_SPI2, + PERIPH_ID_SPI3, + PERIPH_ID_SPI4, PERIPH_ID_UART0, PERIPH_ID_UART1, PERIPH_ID_UART2,