From patchwork Tue Jul 31 09:30:37 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurence Withers X-Patchwork-Id: 174186 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id A2C522C0078 for ; Tue, 31 Jul 2012 19:32:52 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 25C7328111; Tue, 31 Jul 2012 11:32:23 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 1pClkLMl6rJC; Tue, 31 Jul 2012 11:32:22 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A48242811E; Tue, 31 Jul 2012 11:31:35 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 50B7A280F9 for ; Tue, 31 Jul 2012 11:31:28 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Qj4r0ztpRVlH for ; Tue, 31 Jul 2012 11:31:27 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from chrysocolla.lwithers.me.uk (chrysocolla.lwithers.me.uk [80.68.94.184]) by theia.denx.de (Postfix) with ESMTPS id BB5B4280F1 for ; Tue, 31 Jul 2012 11:31:11 +0200 (CEST) Received: from 4.b.0.2.4.9.e.f.f.f.5.6.f.6.e.1.0.0.0.0.5.a.1.0.0.b.8.0.1.0.0.2.ip6.arpa ([2001:8b0:1a5:0:1e6f:65ff:fe94:20b4] helo=rhodium.platinum.guralp.com) by chrysocolla.lwithers.me.uk with esmtpsa (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1Sw8nC-0004Pe-C9; Tue, 31 Jul 2012 09:31:08 +0000 Received: from lwithers by rhodium.platinum.guralp.com with local (Exim 4.72) (envelope-from ) id 1Sw8nB-0004Yi-Vj; Tue, 31 Jul 2012 09:31:05 +0000 From: Laurence Withers To: u-boot@lists.denx.de Date: Tue, 31 Jul 2012 09:30:37 +0000 Message-Id: <1343727037-17419-5-git-send-email-lwithers@guralp.com> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1343727037-17419-1-git-send-email-lwithers@guralp.com> References: <1343727037-17419-1-git-send-email-lwithers@guralp.com> X-SA-Exim-Connect-IP: 2001:8b0:1a5:0:1e6f:65ff:fe94:20b4 X-SA-Exim-Mail-From: lwithers@guralp.com X-SA-Exim-Version: 4.2.1 (built Mon, 22 Mar 2010 06:51:10 +0000) X-SA-Exim-Scanned: Yes (on chrysocolla.lwithers.me.uk) Cc: Tom Rini , Heiko Schocher Subject: [U-Boot] [PATCH v2 4/4] DaVinci DA8xx: fix set_cpu_clk_info() X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de For the DA8xx family of SoCs, the set_cpu_clk_info() function was not initialising the DSP frequency, leading to 'bdinfo' command output such as: [...snip...] ARM frequency = 300 MHz DSP frequency = -536870913 MHz DDR frequency = 300 MHz This commit provides a separate implementation of set_cpu_clk_info() for the DA8xx SoCs that initialises the DSP frequency to zero (since currently the DSP is not enabled by U-Boot on any DA8xx platform). The separate implementation is justified because there is no common code between DA8xx and the other SoC families. It is now much easier to understand the flow of the two separate functions. Signed-off-by: Laurence Withers Cc: Tom Rini Cc: Hadli, Manjunath Cc: Heiko Schocher --- Changes in v2: - Re-ordered patch series to tidy up clock IDs before tidying up users (set_cpu_clk_info()). --- arch/arm/cpu/arm926ejs/davinci/cpu.c | 23 ++++++++++++++--------- 1 files changed, 14 insertions(+), 9 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c b/arch/arm/cpu/arm926ejs/davinci/cpu.c index 41201d0..b31add8 100644 --- a/arch/arm/cpu/arm926ejs/davinci/cpu.c +++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c @@ -117,6 +117,17 @@ int clk_get(enum davinci_clk_ids id) out: return pll_out; } + +int set_cpu_clk_info(void) +{ + gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000; + /* DDR PHY uses an x2 input clock */ + gd->bd->bi_ddr_freq = cpu_is_da830() ? 0 : + (clk_get(DAVINCI_DDR_CLKID) / 1000000); + gd->bd->bi_dsp_freq = 0; + return 0; +} + #else /* CONFIG_SOC_DA8XX */ static unsigned pll_div(volatile void *pllbase, unsigned offset) @@ -187,17 +198,9 @@ unsigned int davinci_clk_get(unsigned int div) return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 1000000; } #endif -#endif /* !CONFIG_SOC_DA8XX */ int set_cpu_clk_info(void) { -#ifdef CONFIG_SOC_DA8XX - gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000; - /* DDR PHY uses an x2 input clock */ - gd->bd->bi_ddr_freq = cpu_is_da830() ? 0 : - (clk_get(DAVINCI_DDR_CLKID) / 1000000); -#else - unsigned int pllbase = DAVINCI_PLL_CNTRL0_BASE; #if defined(CONFIG_SOC_DM365) pllbase = DAVINCI_PLL_CNTRL1_BASE; @@ -216,10 +219,12 @@ int set_cpu_clk_info(void) pllbase = DAVINCI_PLL_CNTRL0_BASE; #endif gd->bd->bi_ddr_freq = pll_sysclk_mhz(pllbase, DDR_PLLDIV) / 2; -#endif + return 0; } +#endif /* !CONFIG_SOC_DA8XX */ + /* * Initializes on-chip ethernet controllers. * to override, implement board_eth_init()