From patchwork Mon Jul 30 16:48:57 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Rini X-Patchwork-Id: 174057 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 4343B2C007C for ; Tue, 31 Jul 2012 02:51:46 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id EA59428126; Mon, 30 Jul 2012 18:50:45 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id tsgLn+zor8Rp; Mon, 30 Jul 2012 18:50:45 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2718E280EA; Mon, 30 Jul 2012 18:49:33 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 16BC42808F for ; Mon, 30 Jul 2012 18:49:19 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 7C5Fiv57Givl for ; Mon, 30 Jul 2012 18:49:18 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-yx0-f172.google.com (mail-yx0-f172.google.com [209.85.213.172]) by theia.denx.de (Postfix) with ESMTPS id 3D6D528097 for ; Mon, 30 Jul 2012 18:49:17 +0200 (CEST) Received: by mail-yx0-f172.google.com with SMTP id q13so4951047yen.3 for ; Mon, 30 Jul 2012 09:49:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:subject:date:message-id:x-mailer:in-reply-to :references; bh=5/6/2VcFrCH+YUJaKqz+eeemgMKNGrRJp6sZR8BkEWo=; b=c8Jv28GlgLcF+mTF8Z5KbSo2JcoxqqeyWEuTcV8qk0uCOoczGyzxyOScMY3hfvMRl7 rll27keAyFByoXFhG2oHww9N3TPM+s94q6nJe1OYvKZ83vSPwwLONz+TNCJV6VvzoY6A iVVnhRnZ+M3Gr6zW2XETgDzBrK+Bxk/euKybTi7LwerV4N1GBtVtdQzxoGrHUxPpgZ7U Mys/83khNCt5BrhzEda45sNa7RNIK4reNpkaIl2CXvK6cCICoqZBNZPlTdDUIV0oy8go rzg4netElT4RnJIY0FyeJCz1qw7sJe+LWZ0MNd2XrIb3IhhOYgcbkr4OLOE0alG9XDHq bJEg== Received: by 10.66.73.132 with SMTP id l4mr26070824pav.30.1343666957406; Mon, 30 Jul 2012 09:49:17 -0700 (PDT) Received: from localhost.localdomain (ip68-230-54-74.ph.ph.cox.net. [68.230.54.74]) by mx.google.com with ESMTPS id ny4sm8227805pbb.57.2012.07.30.09.49.16 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 30 Jul 2012 09:49:16 -0700 (PDT) From: Tom Rini To: u-boot@lists.denx.de Date: Mon, 30 Jul 2012 09:48:57 -0700 Message-Id: <1343666943-25378-12-git-send-email-trini@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1343666943-25378-1-git-send-email-trini@ti.com> References: <1343666943-25378-1-git-send-email-trini@ti.com> Subject: [U-Boot] [PATCH 11/17] am33xx: Clean up unused DDR defines, prefix more with 'DDR2' X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de - Remove a handful of unused defines. - Prefix more values with 'DDR2' as DDR3 will require different values. Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/am33xx/emif4.c | 46 +++++++++++++-------------- arch/arm/include/asm/arch-am33xx/ddr_defs.h | 32 +++++++------------ 2 files changed, 35 insertions(+), 43 deletions(-) diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c index 12f270a..684b123 100644 --- a/arch/arm/cpu/armv7/am33xx/emif4.c +++ b/arch/arm/cpu/armv7/am33xx/emif4.c @@ -112,22 +112,22 @@ static void config_emif_ddr2(void) struct sdram_timing tmg; struct ddr_phy_control phyc; - /*Program EMIF0 CFG Registers*/ - phyc.reg = EMIF_READ_LATENCY; - phyc.reg_sh = EMIF_READ_LATENCY; - phyc.reg2 = EMIF_READ_LATENCY; - - tmg.time1 = EMIF_TIM1; - tmg.time1_sh = EMIF_TIM1; - tmg.time2 = EMIF_TIM2; - tmg.time2_sh = EMIF_TIM2; - tmg.time3 = EMIF_TIM3; - tmg.time3_sh = EMIF_TIM3; - - cfg.sdrcr = EMIF_SDCFG; - cfg.sdrcr2 = EMIF_SDCFG; - cfg.refresh = EMIF_SDREF; - cfg.refresh_sh = EMIF_SDREF; + /* Program EMIF0 CFG Registers */ + phyc.reg = DDR2_EMIF_READ_LATENCY; + phyc.reg_sh = DDR2_EMIF_READ_LATENCY; + phyc.reg2 = DDR2_EMIF_READ_LATENCY; + + tmg.time1 = DDR2_EMIF_TIM1; + tmg.time1_sh = DDR2_EMIF_TIM1; + tmg.time2 = DDR2_EMIF_TIM2; + tmg.time2_sh = DDR2_EMIF_TIM2; + tmg.time3 = DDR2_EMIF_TIM3; + tmg.time3_sh = DDR2_EMIF_TIM3; + + cfg.sdrcr = DDR2_EMIF_SDCFG; + cfg.sdrcr2 = DDR2_EMIF_SDCFG; + cfg.refresh = DDR2_EMIF_SDREF; + cfg.refresh_sh = DDR2_EMIF_SDREF; /* Program EMIF instance */ ret = config_ddr_phy(&phyc); @@ -159,14 +159,14 @@ void config_ddr(short ddr_type) config_ddr_data(0, &ddr2_data); config_ddr_data(1, &ddr2_data); - writel(PHY_RANK0_DELAY, &ddrregs->dt0rdelays0); - writel(PHY_RANK0_DELAY, &ddrregs->dt1rdelays0); + writel(DDR2_PHY_RANK0_DELAY, &ddrregs->dt0rdelays0); + writel(DDR2_PHY_RANK0_DELAY, &ddrregs->dt1rdelays0); - ioctrl.cmd1ctl = DDR_IOCTRL_VALUE; - ioctrl.cmd2ctl = DDR_IOCTRL_VALUE; - ioctrl.cmd3ctl = DDR_IOCTRL_VALUE; - ioctrl.data1ctl = DDR_IOCTRL_VALUE; - ioctrl.data2ctl = DDR_IOCTRL_VALUE; + ioctrl.cmd1ctl = DDR2_IOCTRL_VALUE; + ioctrl.cmd2ctl = DDR2_IOCTRL_VALUE; + ioctrl.cmd3ctl = DDR2_IOCTRL_VALUE; + ioctrl.data1ctl = DDR2_IOCTRL_VALUE; + ioctrl.data2ctl = DDR2_IOCTRL_VALUE; config_io_ctrl(&ioctrl); diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 842e45f..b4735ba 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -22,38 +22,30 @@ #include /* AM335X EMIF Register values */ -#define EMIF_SDMGT 0x80000000 -#define EMIF_SDRAM 0x00004650 -#define EMIF_PHYCFG 0x2 -#define DDR_PHY_RESET (0x1 << 10) -#define DDR_FUNCTIONAL_MODE_EN 0x1 -#define DDR_PHY_READY (0x1 << 2) #define VTP_CTRL_READY (0x1 << 5) #define VTP_CTRL_ENABLE (0x1 << 6) -#define VTP_CTRL_LOCK_EN (0x1 << 4) #define VTP_CTRL_START_EN (0x1) -#define DDR2_RATIO 0x80 #define CMD_FORCE 0x00 #define CMD_DELAY 0x00 +#define PHY_DLL_LOCK_DIFF 0x0 -#define EMIF_READ_LATENCY 0x05 -#define EMIF_TIM1 0x0666B3D6 -#define EMIF_TIM2 0x143731DA -#define EMIF_TIM3 0x00000347 -#define EMIF_SDCFG 0x43805332 -#define EMIF_SDREF 0x0000081a +#define DDR2_EMIF_READ_LATENCY 0x05 +#define DDR2_EMIF_TIM1 0x0666B3D6 +#define DDR2_EMIF_TIM2 0x143731DA +#define DDR2_EMIF_TIM3 0x00000347 +#define DDR2_EMIF_SDCFG 0x43805332 +#define DDR2_EMIF_SDREF 0x0000081a #define DDR2_DLL_LOCK_DIFF 0x0 -#define DDR2_RD_DQS 0x12 -#define DDR2_PHY_FIFO_WE 0x80 - +#define DDR2_RATIO 0x80 #define DDR2_INVERT_CLKOUT 0x00 +#define DDR2_RD_DQS 0x12 #define DDR2_WR_DQS 0x00 #define DDR2_PHY_WRLVL 0x00 #define DDR2_PHY_GATELVL 0x00 #define DDR2_PHY_WR_DATA 0x40 -#define PHY_RANK0_DELAY 0x01 -#define PHY_DLL_LOCK_DIFF 0x0 -#define DDR_IOCTRL_VALUE 0x18B +#define DDR2_PHY_FIFO_WE 0x80 +#define DDR2_PHY_RANK0_DELAY 0x1 +#define DDR2_IOCTRL_VALUE 0x18B /** * Encapsulates DDR PHY control and corresponding shadow registers.