From patchwork Tue Jul 17 13:44:22 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Macpaul Lin X-Patchwork-Id: 171431 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 0EAAF2C00B9 for ; Tue, 17 Jul 2012 23:44:29 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0AC522807E; Tue, 17 Jul 2012 15:44:26 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id J3avEFAv2Wto; Tue, 17 Jul 2012 15:44:25 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4F72D2807F; Tue, 17 Jul 2012 15:44:23 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5F6642807F for ; Tue, 17 Jul 2012 15:44:21 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id TxNmNIIpDr2q for ; Tue, 17 Jul 2012 15:44:20 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-yw0-f44.google.com (mail-yw0-f44.google.com [209.85.213.44]) by theia.denx.de (Postfix) with ESMTPS id 0EC982807E for ; Tue, 17 Jul 2012 15:44:18 +0200 (CEST) Received: by yhq56 with SMTP id 56so371780yhq.3 for ; Tue, 17 Jul 2012 06:44:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=kKXfnfUtzYq5hG+ZNn4VZOPZbPwsxcQNw3LgxaOl5J0=; b=BTYPxSBLX5GHq0oWT9OeRhDBWSq9vvlUeYQcNxh6EqEh6s+d7gz6nhsH3B9FFWEtQy uki0i7WRVhuZUJ0L0EbmT6/5Lax4jXAnwK2LZ1OI1dRTRDGT8D1B1wZhQDC8Zb6QAYcL p4Q/p6FD29qOoC5/GingDAZjLFfV2kOrZUpQyhSBSn8MmgRoU7jtkzqqjM5ZwwN9DgLK wCImwFH5lyW5jYfXEK9ZHr0J5KdkdrD1rTpRodTlHOmKsXaE/9Of6afpKddR+gqV2l+q qD6cTj/dZCdp+VQXMWMe/jSSPS6jnBJDB9TR5jF1ovqtMZzQWb2XuFsJjvS+mnCODZWN eM7Q== Received: by 10.66.81.106 with SMTP id z10mr5530763pax.26.1342532656615; Tue, 17 Jul 2012 06:44:16 -0700 (PDT) Received: from clanlab.dyndns.org ([140.119.175.157]) by mx.google.com with ESMTPS id qc5sm14090008pbb.6.2012.07.17.06.44.14 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 17 Jul 2012 06:44:15 -0700 (PDT) From: Macpaul Lin To: Marek Vasut , u-boot@lists.denx.de, vapier@gentoo.org, wd@denx.de Date: Tue, 17 Jul 2012 21:44:22 +0800 Message-Id: <1342532662-19757-1-git-send-email-macpaul@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: Subject: [U-Boot] [PATCH v2] nds32: split common cache access from cpu into lib X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This commit does the following updates. 1. Split the common cache access from cpu.c into lib folder. 2. Rename the following cache api to adapt common.h - dcache_flush_rang -> flush_dcache_rang - icache_inval_range -> invalidate_icache_range 3. Add invalidate_dcache_range Signed-off-by: Macpaul Lin --- Changes for v2: - flush_dcache_range: merge two asm calls into a single asm volatile() block. - Replace __asm__ __volatile__ block into asm volatile() arch/nds32/cpu/n1213/ag101/cpu.c | 112 --------------------------- arch/nds32/cpu/n1213/ag102/cpu.c | 112 --------------------------- arch/nds32/lib/Makefile | 2 +- arch/nds32/lib/cache.c | 157 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 158 insertions(+), 225 deletions(-) create mode 100644 arch/nds32/lib/cache.c diff --git a/arch/nds32/cpu/n1213/ag101/cpu.c b/arch/nds32/cpu/n1213/ag101/cpu.c index c2636b1..a9991e7 100644 --- a/arch/nds32/cpu/n1213/ag101/cpu.c +++ b/arch/nds32/cpu/n1213/ag101/cpu.c @@ -82,115 +82,3 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /*NOTREACHED*/ } - -static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache) -{ - if (cache == ICACHE) - return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \ - >> ICM_CFG_OFF_ISZ) - 1); - else - return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \ - >> DCM_CFG_OFF_DSZ) - 1); -} - -void dcache_flush_range(unsigned long start, unsigned long end) -{ - unsigned long line_size; - - line_size = CACHE_LINE_SIZE(DCACHE); - - while (end > start) { - __asm__ volatile ("\n\tcctl %0, L1D_VA_WB" : : "r"(start)); - __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL" : : "r"(start)); - start += line_size; - } -} - -void icache_inval_range(unsigned long start, unsigned long end) -{ - unsigned long line_size; - - line_size = CACHE_LINE_SIZE(ICACHE); - while (end > start) { - __asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL" : : "r"(start)); - start += line_size; - } -} - -void flush_cache(unsigned long addr, unsigned long size) -{ - dcache_flush_range(addr, addr + size); - icache_inval_range(addr, addr + size); -} - -void icache_enable(void) -{ - __asm__ __volatile__ ( - "mfsr $p0, $mr8\n\t" - "ori $p0, $p0, 0x01\n\t" - "mtsr $p0, $mr8\n\t" - "isb\n\t" - ); -} - -void icache_disable(void) -{ - __asm__ __volatile__ ( - "mfsr $p0, $mr8\n\t" - "li $p1, ~0x01\n\t" - "and $p0, $p0, $p1\n\t" - "mtsr $p0, $mr8\n\t" - "isb\n\t" - ); -} - -int icache_status(void) -{ - int ret; - - __asm__ __volatile__ ( - "mfsr $p0, $mr8\n\t" - "andi %0, $p0, 0x01\n\t" - : "=r" (ret) - : - : "memory" - ); - - return ret; -} - -void dcache_enable(void) -{ - __asm__ __volatile__ ( - "mfsr $p0, $mr8\n\t" - "ori $p0, $p0, 0x02\n\t" - "mtsr $p0, $mr8\n\t" - "isb\n\t" - ); -} - -void dcache_disable(void) -{ - __asm__ __volatile__ ( - "mfsr $p0, $mr8\n\t" - "li $p1, ~0x02\n\t" - "and $p0, $p0, $p1\n\t" - "mtsr $p0, $mr8\n\t" - "isb\n\t" - ); -} - -int dcache_status(void) -{ - int ret; - - __asm__ __volatile__ ( - "mfsr $p0, $mr8\n\t" - "andi %0, $p0, 0x02\n\t" - : "=r" (ret) - : - : "memory" - ); - - return ret; -} diff --git a/arch/nds32/cpu/n1213/ag102/cpu.c b/arch/nds32/cpu/n1213/ag102/cpu.c index ed88b52..252b69d 100644 --- a/arch/nds32/cpu/n1213/ag102/cpu.c +++ b/arch/nds32/cpu/n1213/ag102/cpu.c @@ -81,115 +81,3 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /*NOTREACHED*/ } - -static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache) -{ - if (cache == ICACHE) - return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \ - >> ICM_CFG_OFF_ISZ) - 1); - else - return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \ - >> DCM_CFG_OFF_DSZ) - 1); -} - -void dcache_flush_range(unsigned long start, unsigned long end) -{ - unsigned long line_size; - - line_size = CACHE_LINE_SIZE(DCACHE); - - while (end > start) { - __asm__ volatile ("\n\tcctl %0, L1D_VA_WB" : : "r"(start)); - __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL" : : "r"(start)); - start += line_size; - } -} - -void icache_inval_range(unsigned long start, unsigned long end) -{ - unsigned long line_size; - - line_size = CACHE_LINE_SIZE(ICACHE); - while (end > start) { - __asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL" : : "r"(start)); - start += line_size; - } -} - -void flush_cache(unsigned long addr, unsigned long size) -{ - dcache_flush_range(addr, addr + size); - icache_inval_range(addr, addr + size); -} - -void icache_enable(void) -{ - __asm__ __volatile__ ( - "mfsr $p0, $mr8\n\t" - "ori $p0, $p0, 0x01\n\t" - "mtsr $p0, $mr8\n\t" - "isb\n\t" - ); -} - -void icache_disable(void) -{ - __asm__ __volatile__ ( - "mfsr $p0, $mr8\n\t" - "li $p1, ~0x01\n\t" - "and $p0, $p0, $p1\n\t" - "mtsr $p0, $mr8\n\t" - "isb\n\t" - ); -} - -int icache_status(void) -{ - int ret; - - __asm__ __volatile__ ( - "mfsr $p0, $mr8\n\t" - "andi %0, $p0, 0x01\n\t" - : "=r" (ret) - : - : "memory" - ); - - return ret; -} - -void dcache_enable(void) -{ - __asm__ __volatile__ ( - "mfsr $p0, $mr8\n\t" - "ori $p0, $p0, 0x02\n\t" - "mtsr $p0, $mr8\n\t" - "isb\n\t" - ); -} - -void dcache_disable(void) -{ - __asm__ __volatile__ ( - "mfsr $p0, $mr8\n\t" - "li $p1, ~0x02\n\t" - "and $p0, $p0, $p1\n\t" - "mtsr $p0, $mr8\n\t" - "isb\n\t" - ); -} - -int dcache_status(void) -{ - int ret; - - __asm__ __volatile__ ( - "mfsr $p0, $mr8\n\t" - "andi %0, $p0, 0x02\n\t" - : "=r" (ret) - : - : "memory" - ); - - return ret; -} diff --git a/arch/nds32/lib/Makefile b/arch/nds32/lib/Makefile index e5c31c3..581a2e7 100644 --- a/arch/nds32/lib/Makefile +++ b/arch/nds32/lib/Makefile @@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(ARCH).o -OBJS := board.o bootm.o interrupts.o +OBJS := board.o bootm.o cache.o interrupts.o all: $(LIB) diff --git a/arch/nds32/lib/cache.c b/arch/nds32/lib/cache.c new file mode 100644 index 0000000..0f1a886 --- /dev/null +++ b/arch/nds32/lib/cache.c @@ -0,0 +1,157 @@ +/* + * Copyright (C) 2012 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation + * Macpaul Lin, Andes Technology Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include + +static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache) +{ + if (cache == ICACHE) + return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \ + >> ICM_CFG_OFF_ISZ) - 1); + else + return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \ + >> DCM_CFG_OFF_DSZ) - 1); +} + +void flush_dcache_range(unsigned long start, unsigned long end) +{ + unsigned long line_size; + + line_size = CACHE_LINE_SIZE(DCACHE); + + while (end > start) { + asm volatile ( + "\n\tcctl %0, L1D_VA_WB" + "\n\tcctl %0, L1D_VA_INVAL" + : + : "r" (start) + ); + start += line_size; + } +} + +void invalidate_icache_range(unsigned long start, unsigned long end) +{ + unsigned long line_size; + + line_size = CACHE_LINE_SIZE(ICACHE); + while (end > start) { + asm volatile ( + "\n\tcctl %0, L1I_VA_INVAL" + : + : "r"(start) + ); + start += line_size; + } +} + +void invalidate_dcache_range(unsigned long start, unsigned long end) +{ + unsigned long line_size; + + line_size = CACHE_LINE_SIZE(DCACHE); + while (end > start) { + asm volatile ( + "\n\tcctl %0, L1D_VA_INVAL" + : + : "r"(start) + ); + start += line_size; + } +} + +void flush_cache(unsigned long addr, unsigned long size) +{ + flush_dcache_range(addr, addr + size); + invalidate_icache_range(addr, addr + size); +} + +void icache_enable(void) +{ + asm volatile ( + "mfsr $p0, $mr8\n\t" + "ori $p0, $p0, 0x01\n\t" + "mtsr $p0, $mr8\n\t" + "isb\n\t" + ); +} + +void icache_disable(void) +{ + asm volatile ( + "mfsr $p0, $mr8\n\t" + "li $p1, ~0x01\n\t" + "and $p0, $p0, $p1\n\t" + "mtsr $p0, $mr8\n\t" + "isb\n\t" + ); +} + +int icache_status(void) +{ + int ret; + + asm volatile ( + "mfsr $p0, $mr8\n\t" + "andi %0, $p0, 0x01\n\t" + : "=r" (ret) + : + : "memory" + ); + + return ret; +} + +void dcache_enable(void) +{ + asm volatile ( + "mfsr $p0, $mr8\n\t" + "ori $p0, $p0, 0x02\n\t" + "mtsr $p0, $mr8\n\t" + "isb\n\t" + ); +} + +void dcache_disable(void) +{ + asm volatile ( + "mfsr $p0, $mr8\n\t" + "li $p1, ~0x02\n\t" + "and $p0, $p0, $p1\n\t" + "mtsr $p0, $mr8\n\t" + "isb\n\t" + ); +} + +int dcache_status(void) +{ + int ret; + + asm volatile ( + "mfsr $p0, $mr8\n\t" + "andi %0, $p0, 0x02\n\t" + : "=r" (ret) + : + : "memory" + ); + + return ret; +}