diff --git a/arch/arm/cpu/arm1176/s3c64xx/reset.S b/arch/arm/cpu/arm1176/s3c64xx/reset.S
index eae572e..9e5ee84 100644
--- a/arch/arm/cpu/arm1176/s3c64xx/reset.S
+++ b/arch/arm/cpu/arm1176/s3c64xx/reset.S
@@ -26,9 +26,9 @@
 .globl reset_cpu
 reset_cpu:
 	ldr	r1, =ELFIN_CLOCK_POWER_BASE
-	ldr	r2, [r1, #SYS_ID_OFFSET]
+	ldr	r2, [r1, #0x118]	@ SYS_ID_OFFSET
 	ldr	r3, =0xffff
 	and	r2, r3, r2, lsr #12
-	str	r2, [r1, #SW_RST_OFFSET]
+	str	r2, [r1, #0x114]	@ SW_RST_OFFSET
 _loop_forever:
 	b	_loop_forever
diff --git a/arch/arm/cpu/arm1176/s3c64xx/speed.c b/arch/arm/cpu/arm1176/s3c64xx/speed.c
index 11962ac..05b44b9 100644
--- a/arch/arm/cpu/arm1176/s3c64xx/speed.c
+++ b/arch/arm/cpu/arm1176/s3c64xx/speed.c
@@ -31,12 +31,13 @@
  */
 
 #include <common.h>
+#include <asm/io.h>
 #include <asm/arch/s3c6400.h>
+#include <asm/arch/clock.h>
 
 #define APLL 0
 #define MPLL 1
 #define EPLL 2
-
 /* ------------------------------------------------------------------------- */
 /*
  * NOTE: This describes the proper use of this file.
@@ -50,17 +51,20 @@
 
 static ulong get_PLLCLK(int pllreg)
 {
+	struct s3c64xx_clock *clk =
+		(struct s3c64xx_clock *)s3c64xx_get_base_clock();
+
 	ulong r, m, p, s;
 
 	switch (pllreg) {
 	case APLL:
-		r = APLL_CON_REG;
+		r = readl(&clk->apll_con);
 		break;
 	case MPLL:
-		r = MPLL_CON_REG;
+		r = readl(&clk->mpll_con);
 		break;
 	case EPLL:
-		r = EPLL_CON0_REG;
+		r = readl(&clk->epll_con0);
 		break;
 	default:
 		hang();
@@ -76,9 +80,11 @@ static ulong get_PLLCLK(int pllreg)
 /* return ARMCORE frequency */
 ulong get_ARMCLK(void)
 {
+	struct s3c64xx_clock *clk =
+		(struct s3c64xx_clock *)s3c64xx_get_base_clock();
 	ulong div;
 
-	div = CLK_DIV0_REG;
+	div = readl(&clk->clk_div0);
 
 	return get_PLLCLK(APLL) / ((div & 0x7) + 1);
 }
@@ -92,16 +98,20 @@ ulong get_FCLK(void)
 /* return HCLK frequency */
 ulong get_HCLK(void)
 {
+	struct s3c64xx_clock *clk =
+		(struct s3c64xx_clock *)s3c64xx_get_base_clock();
 	ulong fclk;
+	ulong other;
 
-	uint hclkx2_div = ((CLK_DIV0_REG >> 9) & 0x7) + 1;
-	uint hclk_div = ((CLK_DIV0_REG >> 8) & 0x1) + 1;
+	uint hclkx2_div = ((readl(&clk->clk_div0) >> 9) & 0x7) + 1;
+	uint hclk_div = ((readl(&clk->clk_div0) >> 8) & 0x1) + 1;
 
 	/*
 	 * Bit 7 exists on s3c6410, and not on s3c6400, it is reserved on
 	 * s3c6400 and is always 0, and it is indeed running in ASYNC mode
 	 */
-	if (OTHERS_REG & 0x80)
+	other = readl(&clk->others);
+	if (other & 0x80)
 		fclk = get_FCLK();		/* SYNC Mode	*/
 	else
 		fclk = get_PLLCLK(MPLL);	/* ASYNC Mode	*/
@@ -112,11 +122,15 @@ ulong get_HCLK(void)
 /* return PCLK frequency */
 ulong get_PCLK(void)
 {
+	struct s3c64xx_clock *clk =
+		(struct s3c64xx_clock *)s3c64xx_get_base_clock();
 	ulong fclk;
-	uint hclkx2_div = ((CLK_DIV0_REG >> 9) & 0x7) + 1;
-	uint pre_div = ((CLK_DIV0_REG >> 12) & 0xf) + 1;
+	uint hclkx2_div = ((readl(&clk->clk_div0) >> 9) & 0x7) + 1;
+	uint pre_div = ((readl(&clk->clk_div0) >> 12) & 0xf) + 1;
+	ulong other;
 
-	if (OTHERS_REG & 0x80)
+	other = readl(&clk->others);
+	if (other & 0x80)
 		fclk = get_FCLK();		/* SYNC Mode	*/
 	else
 		fclk = get_PLLCLK(MPLL);	/* ASYNC Mode	*/
@@ -132,14 +146,20 @@ ulong get_UCLK(void)
 
 int print_cpuinfo(void)
 {
-	printf("\nCPU:     S3C6400@%luMHz\n", get_ARMCLK() / 1000000);
+	struct s3c64xx_clock *clk =
+		(struct s3c64xx_clock *)s3c64xx_get_base_clock();
+	ulong other;
+
+	printf("\nCPU:     S3C64XX@%luMHz\n", get_ARMCLK() / 1000000);
 	printf("         Fclk = %luMHz, Hclk = %luMHz, Pclk = %luMHz ",
 	       get_FCLK() / 1000000, get_HCLK() / 1000000,
 	       get_PCLK() / 1000000);
 
-	if (OTHERS_REG & 0x80)
-		printf("(SYNC Mode) \n");
+	other = readl(&clk->others);
+	if (other & 0x80)
+		printf("(SYNC Mode)\n");
 	else
-		printf("(ASYNC Mode) \n");
+		printf("(ASYNC Mode)\n");
+
 	return 0;
 }
diff --git a/arch/arm/include/asm/arch-s3c64xx/clock.h b/arch/arm/include/asm/arch-s3c64xx/clock.h
new file mode 100644
index 0000000..83b3651
--- /dev/null
+++ b/arch/arm/include/asm/arch-s3c64xx/clock.h
@@ -0,0 +1,147 @@
+/*
+ * (C) Copyright 2012
+ * Hongbo Zhong <bocui107@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARM_ARCH_CLOCK_H_
+#define __ASM_ARM_ARCH_CLOCK_H_
+
+#ifndef __ASSEMBLY__
+
+#if defined(CONFIG_S3C6400)
+struct s3c64xx_clock {
+	unsigned int	apll_lock;
+	unsigned int	mpll_lock;
+	unsigned int	epll_lock;
+	unsigned int	apll_con;
+	unsigned int	mpll_con;
+	unsigned int	epll_con0;
+	unsigned int	epll_con1;
+	unsigned int	clk_src;
+	unsigned int	clk_div0;
+	unsigned int	clk_div1;
+	unsigned int	clk_div2;
+	unsigned int	clk_out;
+	unsigned int	hclk_gate;
+	unsigned int	pclk_gate;
+	unsigned int	sclk_gate;
+	unsigned char	res1[0xc4];
+	unsigned int	ahb_con0;
+	unsigned int	ahb_con1;
+	unsigned int	ahb_con2;
+	unsigned char	res2[0x04];
+	unsigned int	sdma_sel;
+	unsigned int	sw_rst;
+	unsigned int	sys_id;
+	unsigned char	res3[0x4];
+	unsigned int	mem_sys_cfg;
+	unsigned int	qos_override0;
+	unsigned int	qos_override1;
+	unsigned int	mem_cfg_stat;
+	unsigned char	res4[0x6d4];
+	unsigned int	pwr_cfg;
+	unsigned int	eint_mask;
+	unsigned char	res5[0x4];
+	unsigned int	normal_cfg;
+	unsigned int	stop_cfg;
+	unsigned int	sleep_cfg;
+	unsigned char	res6[0x4];
+	unsigned int	osc_freq;
+	unsigned int	osc_stable;
+	unsigned int	pwr_stable;
+	unsigned char	res7[0x4];
+	unsigned int	mtc_stable;
+	unsigned char	res8[0xcc];
+	unsigned int	others;
+	unsigned int	rst_stat;
+	unsigned int	wakeup_stat;
+	unsigned int	blk_pwr_stat;
+	unsigned int	inf_reg0;
+	unsigned int	inf_reg1;
+	unsigned int	inf_reg2;
+	unsigned int	inf_reg3;
+	unsigned int	inf_reg4;
+	unsigned int	inf_reg5;
+	unsigned int	inf_reg6;
+	unsigned int	inf_reg7;
+};
+
+#else
+struct s3c64xx_clock {
+	unsigned int	apll_lock;
+	unsigned int	mpll_lock;
+	unsigned int	epll_lock;
+	unsigned int	apll_con;
+	unsigned int	mpll_con;
+	unsigned int	epll_con0;
+	unsigned int	epll_con1;
+	unsigned int	clk_src;
+	unsigned int	clk_div0;
+	unsigned int	clk_div1;
+	unsigned int	clk_div2;
+	unsigned int	clk_out;
+	unsigned int	hclk_gate;
+	unsigned int	pclk_gate;
+	unsigned int	sclk_gate;
+	unsigned int	mem0_clk_gate;
+	unsigned char	res1[0xc0];
+	unsigned int	ahb_con0;
+	unsigned int	ahb_con1;
+	unsigned int	ahb_con2;
+	unsigned int	clk_src2;
+	unsigned int	sdma_sel;
+	unsigned char	res2[0x04];
+	unsigned int	sys_id;
+	unsigned char	res3[0x4];
+	unsigned int	mem_sys_cfg;
+	unsigned char	res4[0x4];
+	unsigned int	qos_override1;
+	unsigned int	mem_cfg_stat;
+	unsigned char	res5[0x6d4];
+	unsigned int	pwr_cfg;
+	unsigned int	eint_mask;
+	unsigned char	res6[0x4];
+	unsigned int	normal_cfg;
+	unsigned int	stop_cfg;
+	unsigned int	sleep_cfg;
+	unsigned int	stop_mem_cfg;
+	unsigned int	osc_freq;
+	unsigned int	osc_stable;
+	unsigned int	pwr_stable;
+	unsigned char	res7[0x4];
+	unsigned int	mtc_stable;
+	unsigned char	res8[0x4];
+	unsigned int	misc_con;
+	unsigned char	res9[0xc8];
+	unsigned int	others;
+	unsigned int	rst_stat;
+	unsigned int	wakeup_stat;
+	unsigned int	blk_pwr_stat;
+	unsigned int	inf_reg0;
+	unsigned int	inf_reg1;
+	unsigned int	inf_reg2;
+	unsigned int	inf_reg3;
+	unsigned int	inf_reg4;
+	unsigned int	inf_reg5;
+	unsigned int	inf_reg6;
+	unsigned int	inf_reg7;
+};
+#endif /* CONFIG_S3C6400 */
+#endif /* __ASSEMBLY__ */
+#endif
diff --git a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
index 4da95ca..d15b37b 100644
--- a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
+++ b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h
@@ -42,168 +42,6 @@
 
 #define ELFIN_CLOCK_POWER_BASE	0x7e00f000
 
-/* Clock & Power Controller for mDirac3*/
-#define APLL_LOCK_OFFSET	0x00
-#define MPLL_LOCK_OFFSET	0x04
-#define EPLL_LOCK_OFFSET	0x08
-#define APLL_CON_OFFSET		0x0C
-#define MPLL_CON_OFFSET		0x10
-#define EPLL_CON0_OFFSET	0x14
-#define EPLL_CON1_OFFSET	0x18
-#define CLK_SRC_OFFSET		0x1C
-#define CLK_DIV0_OFFSET		0x20
-#define CLK_DIV1_OFFSET		0x24
-#define CLK_DIV2_OFFSET		0x28
-#define CLK_OUT_OFFSET		0x2C
-#define HCLK_GATE_OFFSET	0x30
-#define PCLK_GATE_OFFSET	0x34
-#define SCLK_GATE_OFFSET	0x38
-#define AHB_CON0_OFFSET		0x100
-#define AHB_CON1_OFFSET		0x104
-#define AHB_CON2_OFFSET		0x108
-#define SELECT_DMA_OFFSET	0x110
-#define SW_RST_OFFSET		0x114
-#define SYS_ID_OFFSET		0x118
-#define MEM_SYS_CFG_OFFSET	0x120
-#define QOS_OVERRIDE0_OFFSET	0x124
-#define QOS_OVERRIDE1_OFFSET	0x128
-#define MEM_CFG_STAT_OFFSET	0x12C
-#define PWR_CFG_OFFSET		0x804
-#define EINT_MASK_OFFSET	0x808
-#define NOR_CFG_OFFSET		0x810
-#define STOP_CFG_OFFSET		0x814
-#define SLEEP_CFG_OFFSET	0x818
-#define OSC_FREQ_OFFSET		0x820
-#define OSC_STABLE_OFFSET	0x824
-#define PWR_STABLE_OFFSET	0x828
-#define FPC_STABLE_OFFSET	0x82C
-#define MTC_STABLE_OFFSET	0x830
-#define OTHERS_OFFSET		0x900
-#define RST_STAT_OFFSET		0x904
-#define WAKEUP_STAT_OFFSET	0x908
-#define BLK_PWR_STAT_OFFSET	0x90C
-#define INF_REG0_OFFSET		0xA00
-#define INF_REG1_OFFSET		0xA04
-#define INF_REG2_OFFSET		0xA08
-#define INF_REG3_OFFSET		0xA0C
-#define INF_REG4_OFFSET		0xA10
-#define INF_REG5_OFFSET		0xA14
-#define INF_REG6_OFFSET		0xA18
-#define INF_REG7_OFFSET		0xA1C
-
-#define OSC_CNT_VAL_OFFSET	0x824
-#define PWR_CNT_VAL_OFFSET	0x828
-#define FPC_CNT_VAL_OFFSET	0x82C
-#define MTC_CNT_VAL_OFFSET	0x830
-
-#define APLL_LOCK_REG		__REG(ELFIN_CLOCK_POWER_BASE + APLL_LOCK_OFFSET)
-#define MPLL_LOCK_REG		__REG(ELFIN_CLOCK_POWER_BASE + MPLL_LOCK_OFFSET)
-#define EPLL_LOCK_REG		__REG(ELFIN_CLOCK_POWER_BASE + EPLL_LOCK_OFFSET)
-#define APLL_CON_REG		__REG(ELFIN_CLOCK_POWER_BASE + APLL_CON_OFFSET)
-#define MPLL_CON_REG		__REG(ELFIN_CLOCK_POWER_BASE + MPLL_CON_OFFSET)
-#define EPLL_CON0_REG		__REG(ELFIN_CLOCK_POWER_BASE + EPLL_CON0_OFFSET)
-#define EPLL_CON1_REG		__REG(ELFIN_CLOCK_POWER_BASE + EPLL_CON1_OFFSET)
-#define CLK_SRC_REG		__REG(ELFIN_CLOCK_POWER_BASE + CLK_SRC_OFFSET)
-#define CLK_DIV0_REG		__REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV0_OFFSET)
-#define CLK_DIV1_REG		__REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV1_OFFSET)
-#define CLK_DIV2_REG		__REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV2_OFFSET)
-#define CLK_OUT_REG		__REG(ELFIN_CLOCK_POWER_BASE + CLK_OUT_OFFSET)
-#define HCLK_GATE_REG		__REG(ELFIN_CLOCK_POWER_BASE + HCLK_GATE_OFFSET)
-#define PCLK_GATE_REG		__REG(ELFIN_CLOCK_POWER_BASE + PCLK_GATE_OFFSET)
-#define SCLK_GATE_REG		__REG(ELFIN_CLOCK_POWER_BASE + SCLK_GATE_OFFSET)
-#define AHB_CON0_REG		__REG(ELFIN_CLOCK_POWER_BASE + AHB_CON0_OFFSET)
-#define AHB_CON1_REG		__REG(ELFIN_CLOCK_POWER_BASE + AHB_CON1_OFFSET)
-#define AHB_CON2_REG		__REG(ELFIN_CLOCK_POWER_BASE + AHB_CON2_OFFSET)
-#define SELECT_DMA_REG		__REG(ELFIN_CLOCK_POWER_BASE + \
-				      SELECT_DMA_OFFSET)
-#define SW_RST_REG		__REG(ELFIN_CLOCK_POWER_BASE + SW_RST_OFFSET)
-#define SYS_ID_REG		__REG(ELFIN_CLOCK_POWER_BASE + SYS_ID_OFFSET)
-#define MEM_SYS_CFG_REG		__REG(ELFIN_CLOCK_POWER_BASE + \
-				      MEM_SYS_CFG_OFFSET)
-#define QOS_OVERRIDE0_REG	__REG(ELFIN_CLOCK_POWER_BASE + \
-				      QOS_OVERRIDE0_OFFSET)
-#define QOS_OVERRIDE1_REG	__REG(ELFIN_CLOCK_POWER_BASE + \
-				      QOS_OVERRIDE1_OFFSET)
-#define MEM_CFG_STAT_REG	__REG(ELFIN_CLOCK_POWER_BASE + \
-				      MEM_CFG_STAT_OFFSET)
-#define PWR_CFG_REG		__REG(ELFIN_CLOCK_POWER_BASE + PWR_CFG_OFFSET)
-#define EINT_MASK_REG		__REG(ELFIN_CLOCK_POWER_BASE + EINT_MASK_OFFSET)
-#define NOR_CFG_REG		__REG(ELFIN_CLOCK_POWER_BASE + NOR_CFG_OFFSET)
-#define STOP_CFG_REG		__REG(ELFIN_CLOCK_POWER_BASE + STOP_CFG_OFFSET)
-#define SLEEP_CFG_REG		__REG(ELFIN_CLOCK_POWER_BASE + SLEEP_CFG_OFFSET)
-#define OSC_FREQ_REG		__REG(ELFIN_CLOCK_POWER_BASE + OSC_FREQ_OFFSET)
-#define OSC_CNT_VAL_REG		__REG(ELFIN_CLOCK_POWER_BASE + \
-				      OSC_CNT_VAL_OFFSET)
-#define PWR_CNT_VAL_REG		__REG(ELFIN_CLOCK_POWER_BASE + \
-				      PWR_CNT_VAL_OFFSET)
-#define FPC_CNT_VAL_REG		__REG(ELFIN_CLOCK_POWER_BASE + \
-				      FPC_CNT_VAL_OFFSET)
-#define MTC_CNT_VAL_REG		__REG(ELFIN_CLOCK_POWER_BASE + \
-				      MTC_CNT_VAL_OFFSET)
-#define OTHERS_REG		__REG(ELFIN_CLOCK_POWER_BASE + OTHERS_OFFSET)
-#define RST_STAT_REG		__REG(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET)
-#define WAKEUP_STAT_REG		__REG(ELFIN_CLOCK_POWER_BASE + \
-				      WAKEUP_STAT_OFFSET)
-#define BLK_PWR_STAT_REG	__REG(ELFIN_CLOCK_POWER_BASE + \
-				      BLK_PWR_STAT_OFFSET)
-#define INF_REG0_REG		__REG(ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET)
-#define INF_REG1_REG		__REG(ELFIN_CLOCK_POWER_BASE + INF_REG1_OFFSET)
-#define INF_REG2_REG		__REG(ELFIN_CLOCK_POWER_BASE + INF_REG2_OFFSET)
-#define INF_REG3_REG		__REG(ELFIN_CLOCK_POWER_BASE + INF_REG3_OFFSET)
-#define INF_REG4_REG		__REG(ELFIN_CLOCK_POWER_BASE + INF_REG4_OFFSET)
-#define INF_REG5_REG		__REG(ELFIN_CLOCK_POWER_BASE + INF_REG5_OFFSET)
-#define INF_REG6_REG		__REG(ELFIN_CLOCK_POWER_BASE + INF_REG6_OFFSET)
-#define INF_REG7_REG		__REG(ELFIN_CLOCK_POWER_BASE + INF_REG7_OFFSET)
-
-#define APLL_LOCK	(ELFIN_CLOCK_POWER_BASE + APLL_LOCK_OFFSET)
-#define MPLL_LOCK	(ELFIN_CLOCK_POWER_BASE + MPLL_LOCK_OFFSET)
-#define EPLL_LOCK	(ELFIN_CLOCK_POWER_BASE + EPLL_LOCK_OFFSET)
-#define APLL_CON	(ELFIN_CLOCK_POWER_BASE + APLL_CON_OFFSET)
-#define MPLL_CON	(ELFIN_CLOCK_POWER_BASE + MPLL_CON_OFFSET)
-#define EPLL_CON0	(ELFIN_CLOCK_POWER_BASE + EPLL_CON0_OFFSET)
-#define EPLL_CON1	(ELFIN_CLOCK_POWER_BASE + EPLL_CON1_OFFSET)
-#define CLK_SRC		(ELFIN_CLOCK_POWER_BASE + CLK_SRC_OFFSET)
-#define CLK_DIV0	(ELFIN_CLOCK_POWER_BASE + CLK_DIV0_OFFSET)
-#define CLK_DIV1	(ELFIN_CLOCK_POWER_BASE + CLK_DIV1_OFFSET)
-#define CLK_DIV2	(ELFIN_CLOCK_POWER_BASE + CLK_DIV2_OFFSET)
-#define CLK_OUT		(ELFIN_CLOCK_POWER_BASE + CLK_OUT_OFFSET)
-#define HCLK_GATE	(ELFIN_CLOCK_POWER_BASE + HCLK_GATE_OFFSET)
-#define PCLK_GATE	(ELFIN_CLOCK_POWER_BASE + PCLK_GATE_OFFSET)
-#define SCLK_GATE	(ELFIN_CLOCK_POWER_BASE + SCLK_GATE_OFFSET)
-#define AHB_CON0	(ELFIN_CLOCK_POWER_BASE + AHB_CON0_OFFSET)
-#define AHB_CON1	(ELFIN_CLOCK_POWER_BASE + AHB_CON1_OFFSET)
-#define AHB_CON2	(ELFIN_CLOCK_POWER_BASE + AHB_CON2_OFFSET)
-#define SELECT_DMA	(ELFIN_CLOCK_POWER_BASE + SELECT_DMA_OFFSET)
-#define SW_RST		(ELFIN_CLOCK_POWER_BASE + SW_RST_OFFSET)
-#define SYS_ID		(ELFIN_CLOCK_POWER_BASE + SYS_ID_OFFSET)
-#define MEM_SYS_CFG	(ELFIN_CLOCK_POWER_BASE + MEM_SYS_CFG_OFFSET)
-#define QOS_OVERRIDE0	(ELFIN_CLOCK_POWER_BASE + QOS_OVERRIDE0_OFFSET)
-#define QOS_OVERRIDE1	(ELFIN_CLOCK_POWER_BASE + QOS_OVERRIDE1_OFFSET)
-#define MEM_CFG_STAT	(ELFIN_CLOCK_POWER_BASE + MEM_CFG_STAT_OFFSET)
-#define PWR_CFG		(ELFIN_CLOCK_POWER_BASE + PWR_CFG_OFFSET)
-#define EINT_MASK	(ELFIN_CLOCK_POWER_BASE + EINT_MASK_OFFSET)
-#define NOR_CFG		(ELFIN_CLOCK_POWER_BASE + NOR_CFG_OFFSET)
-#define STOP_CFG	(ELFIN_CLOCK_POWER_BASE + STOP_CFG_OFFSET)
-#define SLEEP_CFG	(ELFIN_CLOCK_POWER_BASE + SLEEP_CFG_OFFSET)
-#define OSC_FREQ	(ELFIN_CLOCK_POWER_BASE + OSC_FREQ_OFFSET)
-#define OSC_CNT_VAL	(ELFIN_CLOCK_POWER_BASE + OSC_CNT_VAL_OFFSET)
-#define PWR_CNT_VAL	(ELFIN_CLOCK_POWER_BASE + PWR_CNT_VAL_OFFSET)
-#define FPC_CNT_VAL	(ELFIN_CLOCK_POWER_BASE + FPC_CNT_VAL_OFFSET)
-#define MTC_CNT_VAL	(ELFIN_CLOCK_POWER_BASE + MTC_CNT_VAL_OFFSET)
-#define OTHERS		(ELFIN_CLOCK_POWER_BASE + OTHERS_OFFSET)
-#define RST_STAT	(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET)
-#define WAKEUP_STAT	(ELFIN_CLOCK_POWER_BASE + WAKEUP_STAT_OFFSET)
-#define BLK_PWR_STAT	(ELFIN_CLOCK_POWER_BASE + BLK_PWR_STAT_OFFSET)
-#define INF_REG0	(ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET)
-#define INF_REG1	(ELFIN_CLOCK_POWER_BASE + INF_REG1_OFFSET)
-#define INF_REG2	(ELFIN_CLOCK_POWER_BASE + INF_REG2_OFFSET)
-#define INF_REG3	(ELFIN_CLOCK_POWER_BASE + INF_REG3_OFFSET)
-#define INF_REG4	(ELFIN_CLOCK_POWER_BASE + INF_REG4_OFFSET)
-#define INF_REG5	(ELFIN_CLOCK_POWER_BASE + INF_REG5_OFFSET)
-#define INF_REG6	(ELFIN_CLOCK_POWER_BASE + INF_REG6_OFFSET)
-#define INF_REG7	(ELFIN_CLOCK_POWER_BASE + INF_REG7_OFFSET)
-
-
 /*
  * GPIO
  */
@@ -718,6 +556,11 @@ static inline unsigned int s3c64xx_get_base_sromc(void)
 {
 	return ELFIN_SROM_BASE;
 }
+
+static inline unsigned int s3c64xx_get_base_clock(void)
+{
+	return ELFIN_CLOCK_POWER_BASE;
+}
 #endif
 
 #endif /*__S3C6400_H__*/
diff --git a/board/samsung/smdk6400/lowlevel_init.S b/board/samsung/smdk6400/lowlevel_init.S
index 81e5c6a..8a24cc1 100644
--- a/board/samsung/smdk6400/lowlevel_init.S
+++ b/board/samsung/smdk6400/lowlevel_init.S
@@ -106,7 +106,7 @@ lowlevel_init:
 	bl	mem_ctrl_asm_init
 
 /* Wakeup support. Don't know if it's going to be used, untested. */
-	ldr	r0, =(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET)
+	ldr	r0, =(ELFIN_CLOCK_POWER_BASE + 0x904)	@ RST_STAT_OFFSET
 	ldr	r1, [r0]
 	bic	r1, r1, #0xfffffff7
 	cmp	r1, #0x8
@@ -119,23 +119,24 @@ lowlevel_init:
 wakeup_reset:
 
 	/* Clear wakeup status register */
-	ldr	r0, =(ELFIN_CLOCK_POWER_BASE + WAKEUP_STAT_OFFSET)
+	ldr	r0, =(ELFIN_CLOCK_POWER_BASE + 0x908)	@ WAKEUP_STAT_OFFSET
 	ldr	r1, [r0]
 	str	r1, [r0]
 
 	/* LED test */
 	ldr	r0, =ELFIN_GPIO_BASE
 	ldr	r1, =0x3000
-	str	r1, [r0, #GPNDAT_OFFSET]
+	str	r1, [r0, #0x834]		@ GPNDAT_OFFSET
 
 	/* Load return address and jump to kernel */
-	ldr	r0, =(ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET)
+	ldr	r0, =(ELFIN_CLOCK_POWER_BASE + 0xa00)	@ INF_REG0_OFFSET
 	/* r1 = physical address of s3c6400_cpu_resume function */
 	ldr	r1, [r0]
 	/* Jump to kernel (sleep-s3c6400.S) */
 	mov	pc, r1
 	nop
 	nop
+
 /*
  * system_clock_init: Initialize core clock and bus clock.
  * void system_clock_init(void)
@@ -144,10 +145,10 @@ system_clock_init:
 	ldr	r0, =ELFIN_CLOCK_POWER_BASE	/* 0x7e00f000 */
 
 #ifdef CONFIG_SYNC_MODE
-	ldr	r1, [r0, #OTHERS_OFFSET]
+	ldr	r1, [r0, #0x900]	@ OTHERS_OFFSET
 	mov	r2, #0x40
 	orr	r1, r1, r2
-	str	r1, [r0, #OTHERS_OFFSET]
+	str	r1, [r0, #0x900]
 
 	nop
 	nop
@@ -157,10 +158,10 @@ system_clock_init:
 
 	ldr	r2, =0x80
 	orr	r1, r1, r2
-	str	r1, [r0, #OTHERS_OFFSET]
+	str	r1, [r0, #0x900]
 
 check_syncack:
-	ldr	r1, [r0, #OTHERS_OFFSET]
+	ldr	r1, [r0, #0x900]
 	ldr	r2, =0xf00
 	and	r1, r1, r2
 	cmp	r1, #0xf00
@@ -177,69 +178,58 @@ check_syncack:
 	 * seem to make much sense on S3C6400.
 	 */
 #ifndef CONFIG_S3C6400
-	ldr	r1, [r0, #OTHERS_OFFSET]
+	ldr	r1, [r0, #0x900]	@ OTHERS_OFFSET
 	bic	r1, r1, #0xC0
 	orr	r1, r1, #0x40
-	str	r1, [r0, #OTHERS_OFFSET]
+	str	r1, [r0, #0x900]
 
 wait_for_async:
-	ldr	r1, [r0, #OTHERS_OFFSET]
+	ldr	r1, [r0, #0x900]	@ OTHERS_OFFSET
 	and	r1, r1, #0xf00
 	cmp	r1, #0x0
 	bne	wait_for_async
 #endif
 
-	ldr	r1, [r0, #OTHERS_OFFSET]
+	ldr	r1, [r0, #0x900]	@ OTHERS_OFFSET
 	bic	r1, r1, #0x40
-	str	r1, [r0, #OTHERS_OFFSET]
+	str	r1, [r0, #0x900]
 #endif
 
 	mov	r1, #0xff00
 	orr	r1, r1, #0xff
-	str	r1, [r0, #APLL_LOCK_OFFSET]
-	str	r1, [r0, #MPLL_LOCK_OFFSET]
+	str	r1, [r0, #0x0]		@ APLL_LOCK_OFFSET
+	str	r1, [r0, #0x4]		@ MPLL_LOCK_OFFSET
 
 	/* Set Clock Divider */
-	ldr	r1, [r0, #CLK_DIV0_OFFSET]
+	ldr	r1, [r0, #0x20]		@ CLK_DIV0_OFFSET
 	bic	r1, r1, #0x30000
 	bic	r1, r1, #0xff00
 	bic	r1, r1, #0xff
 	ldr	r2, =CLK_DIV_VAL
 	orr	r1, r1, r2
-	str	r1, [r0, #CLK_DIV0_OFFSET]
+	str	r1, [r0, #0x20]
 
 	ldr	r1, =APLL_VAL
-	str	r1, [r0, #APLL_CON_OFFSET]
+	str	r1, [r0, #0x0c]		@ APLL_CON_OFFSET
 	ldr	r1, =MPLL_VAL
-	str	r1, [r0, #MPLL_CON_OFFSET]
+	str	r1, [r0, #0x10]		@ MPLL_CON_OFFSET
 
 	/* FOUT of EPLL is 96MHz */
 	ldr	r1, =0x200203
-	str	r1, [r0, #EPLL_CON0_OFFSET]
+	str	r1, [r0, #0x14]		@ EPLL_CON0_OFFSET
 	ldr	r1, =0x0
-	str	r1, [r0, #EPLL_CON1_OFFSET]
+	str	r1, [r0, #0x18]		@ EPLL_CON1_OFFSET
 
 	/* APLL, MPLL, EPLL select to Fout */
-	ldr	r1, [r0, #CLK_SRC_OFFSET]
+	ldr	r1, [r0, #0x1c]		@ CLK_SRC_OFFSET
 	orr	r1, r1, #0x7
-	str	r1, [r0, #CLK_SRC_OFFSET]
+	str	r1, [r0, #0x1c]
 
 	/* wait at least 200us to stablize all clock */
 	mov	r1, #0x10000
 1:	subs	r1, r1, #1
 	bne	1b
 
-	/* Synchronization for VIC port */
-#if defined(CONFIG_SYNC_MODE)
-	ldr	r1, [r0, #OTHERS_OFFSET]
-	orr	r1, r1, #0x20
-	str	r1, [r0, #OTHERS_OFFSET]
-#elif !defined(CONFIG_S3C6400)
-	/* According to 661558um_S3C6400X_rev10.pdf 0x20 is reserved */
-	ldr	r1, [r0, #OTHERS_OFFSET]
-	bic	r1, r1, #0x20
-	str	r1, [r0, #OTHERS_OFFSET]
-#endif
 	mov	pc, lr
 
 
diff --git a/drivers/usb/host/s3c64xx-hcd.c b/drivers/usb/host/s3c64xx-hcd.c
index cd295da..74b5951 100644
--- a/drivers/usb/host/s3c64xx-hcd.c
+++ b/drivers/usb/host/s3c64xx-hcd.c
@@ -25,21 +25,45 @@
  */
 
 #include <common.h>
+#include <asm/io.h>
 #include <asm/arch/s3c6400.h>
+#include <asm/arch/clock.h>
 
 int usb_cpu_init(void)
 {
-	OTHERS_REG |= 0x10000;
+	unsigned int val;
+	struct s3c64xx_clock *clk =
+			(struct s3c64xx_clock *)s3c64xx_get_base_clock();
+
+	val = readl(&clk->others);
+	val |= 0x10000;
+	writel(val, &clk->others);
+
 	return 0;
 }
 
 int usb_cpu_stop(void)
 {
-	OTHERS_REG &= ~0x10000;
+	unsigned int val;
+	struct s3c64xx_clock *clk =
+			(struct s3c64xx_clock *)s3c64xx_get_base_clock();
+
+	val = readl(&clk->others);
+	val &= ~0x10000;
+	writel(val, &clk->others);
+
 	return 0;
 }
 
 void usb_cpu_init_fail(void)
 {
-	OTHERS_REG &= ~0x10000;
+	unsigned int val;
+	struct s3c64xx_clock *clk =
+			(struct s3c64xx_clock *)s3c64xx_get_base_clock();
+
+	val = readl(&clk->others);
+	val &= ~0x10000;
+	writel(val, &clk->others);
+
+	return 0;
 }
