| Message ID | 1339169212-2417-1-git-send-email-dinguyen@altera.com |
|---|---|
| State | Awaiting Upstream |
| Delegated to: | Joe Hershberger |
| Headers | show |
On 6/8/2012 8:56 PM, Dinh Nguyen wrote: > This commit is an add-on to f6c4191f. There are a few registers where > consecutive writes to the same location should be avoided or have a delay. > > According to Synopsys, here is a list of the registers and bit(s) where > consecutive writes should be avoided or a delay is required: > > DMA Registers: > Register 0 Bit 7 > Register 6 All bits except for 24, 16-13, 2-1. > > GMAC Registers: > Registers 0-3 All bits > Registers 6-7 All bits > Register 10 All bits > Register 11 All bits except for 5-6. > Registers 16-47 All bits > Register 48 All bits except for 18-16, 14. > Register 448 Bit 4. > Register 459 Bits 0-3. > > Reviewd-by: Matthew Gerlach<mgerlach@altera.com> > Signed-off-by: Dinh Nguyen<dinguyen@altera.com> > --- > drivers/net/designware.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/net/designware.c b/drivers/net/designware.c > index e8e669b..980b92f 100644 > --- a/drivers/net/designware.c > +++ b/drivers/net/designware.c > @@ -163,8 +163,8 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis) > writel(FIXEDBURST | PRIORXTX_41 | BURST_16, > &dma_p->busmode); > > - writel(FLUSHTXFIFO | readl(&dma_p->opmode),&dma_p->opmode); > - writel(STOREFORWARD | TXSECONDFRAME,&dma_p->opmode); > + writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD | > + TXSECONDFRAME,&dma_p->opmode); > > conf = FRAMEBURSTENABLE | DISABLERXOWN; > Acked-by: Amit Virdi <amit.virdi@st.com>
Hi Dinh Nguyen, On Fri, Jun 8, 2012 at 10:26 AM, Dinh Nguyen <gills702@gmail.com> wrote: > This commit is an add-on to f6c4191f. There are a few registers where > consecutive writes to the same location should be avoided or have a delay. > > According to Synopsys, here is a list of the registers and bit(s) where > consecutive writes should be avoided or a delay is required: > > DMA Registers: > Register 0 Bit 7 > Register 6 All bits except for 24, 16-13, 2-1. > > GMAC Registers: > Registers 0-3 All bits > Registers 6-7 All bits > Register 10 All bits > Register 11 All bits except for 5-6. > Registers 16-47 All bits > Register 48 All bits except for 18-16, 14. > Register 448 Bit 4. > Register 459 Bits 0-3. > > Reviewd-by: Matthew Gerlach <mgerlach@altera.com> > Signed-off-by: Dinh Nguyen <dinguyen@altera.com> > --- Applied to next, thanks. -Joe
diff --git a/drivers/net/designware.c b/drivers/net/designware.c index e8e669b..980b92f 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -163,8 +163,8 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis) writel(FIXEDBURST | PRIORXTX_41 | BURST_16, &dma_p->busmode); - writel(FLUSHTXFIFO | readl(&dma_p->opmode), &dma_p->opmode); - writel(STOREFORWARD | TXSECONDFRAME, &dma_p->opmode); + writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD | + TXSECONDFRAME, &dma_p->opmode); conf = FRAMEBURSTENABLE | DISABLERXOWN;
This commit is an add-on to f6c4191f. There are a few registers where consecutive writes to the same location should be avoided or have a delay. According to Synopsys, here is a list of the registers and bit(s) where consecutive writes should be avoided or a delay is required: DMA Registers: Register 0 Bit 7 Register 6 All bits except for 24, 16-13, 2-1. GMAC Registers: Registers 0-3 All bits Registers 6-7 All bits Register 10 All bits Register 11 All bits except for 5-6. Registers 16-47 All bits Register 48 All bits except for 18-16, 14. Register 448 Bit 4. Register 459 Bits 0-3. Reviewd-by: Matthew Gerlach <mgerlach@altera.com> Signed-off-by: Dinh Nguyen <dinguyen@altera.com> --- drivers/net/designware.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)