From patchwork Fri Jun 8 13:12:12 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ilya Yanok X-Patchwork-Id: 163784 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 1CC8BB6FBC for ; Fri, 8 Jun 2012 23:59:26 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9F01928246; Fri, 8 Jun 2012 15:59:03 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id pRbIGDArHjeq; Fri, 8 Jun 2012 15:59:03 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D5C4528235; Fri, 8 Jun 2012 15:58:40 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 10DBC2815E for ; Fri, 8 Jun 2012 15:12:35 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id wmXAS2BW9gfP for ; Fri, 8 Jun 2012 15:12:34 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-lb0-f172.google.com (mail-lb0-f172.google.com [209.85.217.172]) by theia.denx.de (Postfix) with ESMTPS id 927982815F for ; Fri, 8 Jun 2012 15:12:34 +0200 (CEST) Received: by mail-lb0-f172.google.com with SMTP id go11so1376448lbb.3 for ; Fri, 08 Jun 2012 06:12:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=7hQAMIq1ZdU+d+yjMcsxwJKkQLGK2ff4ZzGQn6wl5LU=; b=SSDTWCnnUYNGTarzC9bEBemotYOOkjrS0+u1QwEvEKFbJKTMCnn7rg3M+7FSll202F zuYLwPq22x43VPL4qSNhQUoG0PaMUDlwbcKM0H+A5U2c6UVw2DIn9wFVol6DCQpSDkdw vXIP9gjMWLzrvVTgilsPChdvRvK/t3cJ8TftxiI/K0DLh5ZrATvwuGTbOZ1YvaQuj2BG 4D7zuYXBVmtGe5pk1itJ01gfL5zGwALxZL3gMyXs4B4gO9HpisJBrMsgTQ5PKKJ+MXFN /gOcQOaODgUbDlKsxK9b6vLWPIxwGt+KNaVlg9BDLloWS2iZERpul/OAHij3gM5ZVdzv Fv7w== Received: by 10.112.47.104 with SMTP id c8mr3786189lbn.101.1339161154188; Fri, 08 Jun 2012 06:12:34 -0700 (PDT) Received: from orwell.yanok.lan ([188.134.70.194]) by mx.google.com with ESMTPS id fv16sm9647724lab.9.2012.06.08.06.12.33 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 08 Jun 2012 06:12:33 -0700 (PDT) From: Ilya Yanok To: u-boot@lists.denx.de Date: Fri, 8 Jun 2012 17:12:12 +0400 Message-Id: <1339161134-11818-5-git-send-email-ilya.yanok@cogentembedded.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1339161134-11818-1-git-send-email-ilya.yanok@cogentembedded.com> References: <1339161134-11818-1-git-send-email-ilya.yanok@cogentembedded.com> X-Gm-Message-State: ALoCoQkfbHLyJa8UuLGM11Kard9yXjuevCs+Eicp8CSom4UxyibSuCGHeWbLTobTTFmbUkobUpfA X-Mailman-Approved-At: Fri, 08 Jun 2012 15:58:31 +0200 Cc: Tom Rini , Ilya Yanok Subject: [U-Boot] [PATCH 4/6] am33xx: pin mux defintions for CPSW switch X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This patch adds pin mux settings for CPSW switch found on TI AM335X based boards (MII and RGMII modes). CC: Tom Rini Signed-off-by: Ilya Yanok --- arch/arm/include/asm/arch-am33xx/common_def.h | 2 ++ board/ti/am335x/mux.c | 47 +++++++++++++++++++++++++ 2 files changed, 49 insertions(+) diff --git a/arch/arm/include/asm/arch-am33xx/common_def.h b/arch/arm/include/asm/arch-am33xx/common_def.h index aa3b554..5a7b0f3 100644 --- a/arch/arm/include/asm/arch-am33xx/common_def.h +++ b/arch/arm/include/asm/arch-am33xx/common_def.h @@ -19,5 +19,7 @@ extern void enable_uart0_pin_mux(void); extern void enable_mmc0_pin_mux(void); extern void enable_i2c0_pin_mux(void); +extern void enable_mii1_pin_mux(void); +extern void enable_rgmii1_pin_mux(void); #endif/*__COMMON_DEF_H__ */ diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index 9ccb436..327b2de 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -280,6 +280,43 @@ static struct module_pin_mux i2c0_pin_mux[] = { {-1}, }; +static struct module_pin_mux rgmii1_pin_mux[] = { + {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */ + {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */ + {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */ + {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */ + {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */ + {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */ + {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */ + {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */ + {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */ + {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */ + {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */ + {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + +static struct module_pin_mux mii1_pin_mux[] = { + {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */ + {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */ + {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */ + {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */ + {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */ + {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */ + {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */ + {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */ + {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */ + {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */ + {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */ + {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */ + {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + /* * Configure the pin mux for the module */ @@ -310,3 +347,13 @@ void enable_i2c0_pin_mux(void) { configure_module_pin_mux(i2c0_pin_mux); } + +void enable_rgmii1_pin_mux(void) +{ + configure_module_pin_mux(rgmii1_pin_mux); +} + +void enable_mii1_pin_mux(void) +{ + configure_module_pin_mux(mii1_pin_mux); +}