From patchwork Fri Jun 8 13:12:11 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ilya Yanok X-Patchwork-Id: 163783 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 34311B6FBC for ; Fri, 8 Jun 2012 23:59:18 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 248BE28277; Fri, 8 Jun 2012 15:58:57 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id oMKuIE2NJ0B1; Fri, 8 Jun 2012 15:58:56 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 989662823F; Fri, 8 Jun 2012 15:58:39 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id AF58828163 for ; Fri, 8 Jun 2012 15:12:34 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id XBXKOh6k1Mtk for ; Fri, 8 Jun 2012 15:12:34 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-lpp01m010-f44.google.com (mail-lpp01m010-f44.google.com [209.85.215.44]) by theia.denx.de (Postfix) with ESMTPS id 03CD22815E for ; Fri, 8 Jun 2012 15:12:32 +0200 (CEST) Received: by mail-lpp01m010-f44.google.com with SMTP id v3so1264931lag.3 for ; Fri, 08 Jun 2012 06:12:32 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=Ls9cjTe+REk1OeKz875SJV0M9mxdZf9QGNuTxL0AFQc=; b=kKj5ptEHSJFFIfc08fT/xE3MreSd6yeaySvpEE6/Qej+PZxcDw1YDS2c40ADj8/eva QRcrn8x4A7fOJHTChKeRZm0WUG2z2+G9VDEuEfJn90bboHH5ryf5XFq/M0fcP3ZhFf7f mIyt4ZocHtqg2wVn47lNuPKChyIY6tDBgs2I6te50vVDoEIbJytA2ANEiXSrgh5o+QOR F32q2AH+CO8yUAX20+z5Rk6vqMpYBTVIcJYzHDj2vrhCH3D1uLzD58e1lDg+EC+YaG4G nYycprwpSHNB06dKSjlArVsVy4hZ/5vC4/Vz+ec7RxLwgvKqVRi7r7JzNWUq8z49/IZH MYUA== Received: by 10.152.105.173 with SMTP id gn13mr8384655lab.20.1339161152383; Fri, 08 Jun 2012 06:12:32 -0700 (PDT) Received: from orwell.yanok.lan ([188.134.70.194]) by mx.google.com with ESMTPS id fv16sm9647724lab.9.2012.06.08.06.12.31 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 08 Jun 2012 06:12:32 -0700 (PDT) From: Ilya Yanok To: u-boot@lists.denx.de Date: Fri, 8 Jun 2012 17:12:11 +0400 Message-Id: <1339161134-11818-4-git-send-email-ilya.yanok@cogentembedded.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1339161134-11818-1-git-send-email-ilya.yanok@cogentembedded.com> References: <1339161134-11818-1-git-send-email-ilya.yanok@cogentembedded.com> X-Gm-Message-State: ALoCoQn3dAUfnblYxI9bytTJfYtj2lCZE5rsRVTPYBHib32Q8axvpHIPR1TV8N6zjLOtshEEQZpZ X-Mailman-Approved-At: Fri, 08 Jun 2012 15:58:31 +0200 Cc: Tom Rini , Ilya Yanok Subject: [U-Boot] [PATCH 3/6] am33xx: CPSW init and definitions X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This patch adds platform-specific initialization for CPSW switch on TI AM33XX SoCs. CC: Tom Rini Signed-off-by: Ilya Yanok --- arch/arm/cpu/armv7/am33xx/clock.c | 8 +++++++- arch/arm/include/asm/arch-am33xx/cpu.h | 12 ++++++++++++ arch/arm/include/asm/arch-am33xx/hardware.h | 5 +++++ 3 files changed, 24 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c index bbb9c13..3cfdcbd 100644 --- a/arch/arm/cpu/armv7/am33xx/clock.c +++ b/arch/arm/cpu/armv7/am33xx/clock.c @@ -24,6 +24,7 @@ #define PRCM_MOD_EN 0x2 #define PRCM_FORCE_WAKEUP 0x2 +#define PRCM_FUNCTL 0x0 #define PRCM_EMIF_CLK_ACTIVITY BIT(2) #define PRCM_L3_GCLK_ACTIVITY BIT(4) @@ -38,7 +39,7 @@ #define CLK_MODE_SEL 0x7 #define CLK_MODE_MASK 0xfffffff8 #define CLK_DIV_SEL 0xFFFFFFE0 - +#define CPGMAC0_IDLE 0x30000 const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER; const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP; @@ -118,6 +119,11 @@ static void enable_per_clocks(void) writel(PRCM_MOD_EN, &cmwkup->wkup_i2c0ctrl); while (readl(&cmwkup->wkup_i2c0ctrl) != PRCM_MOD_EN) ; + + /* Ethernet */ + writel(PRCM_MOD_EN, &cmper->cpgmac0clkctrl); + while ((readl(&cmper->cpgmac0clkctrl) & CPGMAC0_IDLE) != PRCM_FUNCTL) + ; } static void mpu_pll_config(void) diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 5a6534e..1b41b10 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -233,6 +233,18 @@ struct ctrl_stat { unsigned int resv1[16]; unsigned int statusreg; /* ofset 0x40 */ }; + +/* Control Device Register */ +struct ctrl_dev { + unsigned int deviceid; /* offset 0x00 */ + unsigned int resv1[11]; + unsigned int macid0l; /* offset 0x30 */ + unsigned int macid0h; /* offset 0x34 */ + unsigned int macid1l; /* offset 0x38 */ + unsigned int macid1h; /* offset 0x3c */ + unsigned int resv2[4]; + unsigned int miisel; /* offset 0x50 */ +}; #endif /* __ASSEMBLY__ */ #endif /* __KERNEL_STRICT_NAMES */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h index 0ec22eb..4b1c725 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware.h +++ b/arch/arm/include/asm/arch-am33xx/hardware.h @@ -46,6 +46,7 @@ /* Control Module Base Address */ #define CTRL_BASE 0x44E10000 +#define CTRL_DEVICE_BASE 0x44E10600 /* PRCM Base Address */ #define PRCM_BASE 0x44E00000 @@ -78,4 +79,8 @@ #define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400) #define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE +/* CPSW Config space */ +#define AM335X_CPSW_BASE 0x4A100000 +#define AM335X_CPSW_MDIO_BASE 0x4A101000 + #endif /* __AM33XX_HARDWARE_H */