From patchwork Fri May 18 12:12:26 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajeshwari Birje X-Patchwork-Id: 160100 X-Patchwork-Delegate: hs@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 700C5B6FB7 for ; Fri, 18 May 2012 22:11:13 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 675FD28080; Fri, 18 May 2012 14:11:11 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id L8UOtDIZAsA4; Fri, 18 May 2012 14:11:11 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 51DB728082; Fri, 18 May 2012 14:11:08 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9DCEC28087 for ; Fri, 18 May 2012 14:11:05 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id syx-0JNMiStB for ; Fri, 18 May 2012 14:11:04 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mailout3.samsung.com (mailout3.samsung.com [203.254.224.33]) by theia.denx.de (Postfix) with ESMTP id 5000B28086 for ; Fri, 18 May 2012 14:11:02 +0200 (CEST) Received: from epcpsbgm2.samsung.com (mailout3.samsung.com [203.254.224.33]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M4700G4WWIALR40@mailout3.samsung.com> for u-boot@lists.denx.de; Fri, 18 May 2012 21:10:59 +0900 (KST) X-AuditID: cbfee61b-b7bb6ae0000006fb-6f-4fb63c53444c Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (MMPCPMTA) with SMTP id DF.3F.01787.35C36BF4; Fri, 18 May 2012 21:10:59 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M470045KWF74W10@mmp2.samsung.com> for u-boot@lists.denx.de; Fri, 18 May 2012 21:10:59 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Date: Fri, 18 May 2012 17:42:26 +0530 Message-id: <1337343153-3019-2-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1337343153-3019-1-git-send-email-rajeshwari.s@samsung.com> References: <1337343153-3019-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: AAAAAA== X-TM-AS-MML: No Cc: patches@linaro.org Subject: [U-Boot] [PATCH 1/8] EXYNOS: CLK: Add i2c clock X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This adds i2c clock information for EXYNOS5. Signed-off-by: Alim Akhtar Signed-off-by: Doug Anderson Signed-off-by: Rajeshwari Shinde Acked-by: Simon Glass --- arch/arm/cpu/armv7/exynos/clock.c | 33 ++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/clk.h | 1 + 2 files changed, 34 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 330bd75..3b86b0c 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -578,6 +578,29 @@ void exynos4_set_mipi_clk(void) writel(cfg, &clk->div_lcd0); } +/* + * I2C + * + * exynos5: obtaining the I2C clock + */ +static unsigned long exynos5_get_i2c_clk(void) +{ + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + unsigned long aclk_66, aclk_66_pre, sclk; + unsigned int ratio; + + sclk = get_pll_clk(MPLL); + + ratio = ((readl(&clk->div_top1)) >> 24); + ratio &= (0x7); + aclk_66_pre = sclk/(ratio+1); + ratio = readl(&clk->div_top0); + ratio &= (0x7); + aclk_66 = aclk_66_pre/(ratio+1); + return aclk_66; +} + unsigned long get_pll_clk(int pllreg) { if (cpu_is_exynos5()) @@ -594,6 +617,16 @@ unsigned long get_arm_clk(void) return exynos4_get_arm_clk(); } +unsigned long get_i2c_clk(void) +{ + if (cpu_is_exynos5()) { + return exynos5_get_i2c_clk(); + } else { + debug("I2C clock is not set for this CPU\n"); + return 0; + } +} + unsigned long get_pwm_clk(void) { if (cpu_is_exynos5()) diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index 637fb4b..72dc655 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -30,6 +30,7 @@ unsigned long get_pll_clk(int pllreg); unsigned long get_arm_clk(void); +unsigned long get_i2c_clk(void); unsigned long get_pwm_clk(void); unsigned long get_uart_clk(int dev_index); void set_mmc_clk(int dev_index, unsigned int div);