From patchwork Thu May 17 09:52:54 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: SRICHARAN R X-Patchwork-Id: 159877 X-Patchwork-Delegate: albert.aribaud@free.fr Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id CF01EB6FBD for ; Thu, 17 May 2012 19:53:11 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7EF062807E; Thu, 17 May 2012 11:53:08 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 6m2nmmqLiN09; Thu, 17 May 2012 11:53:07 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 891AD2807F; Thu, 17 May 2012 11:53:06 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7424B2807F for ; Thu, 17 May 2012 11:53:04 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id M71GR6GIywe4 for ; Thu, 17 May 2012 11:53:03 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from arroyo.ext.ti.com (arroyo.ext.ti.com [192.94.94.40]) by theia.denx.de (Postfix) with ESMTPS id 0DFD32807E for ; Thu, 17 May 2012 11:53:01 +0200 (CEST) Received: from dbdp20.itg.ti.com ([172.24.170.38]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id q4H9qvYK010460 for ; Thu, 17 May 2012 04:52:58 -0500 Received: from DBDE70.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id q4H9quiP026978 for ; Thu, 17 May 2012 15:22:57 +0530 (IST) Received: from dbdp31.itg.ti.com (172.24.170.98) by dbde70.ent.ti.com (172.24.170.148) with Microsoft SMTP Server id 14.1.323.3; Thu, 17 May 2012 15:22:56 +0530 Received: from ula0393807.apr.dhcp.ti.com (ula0393807-172024137165.apr.dhcp.ti.com [172.24.137.165]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id q4H9qsPj015787; Thu, 17 May 2012 15:22:56 +0530 (IST) From: R Sricharan To: Date: Thu, 17 May 2012 15:22:54 +0530 Message-ID: <1337248374-23252-1-git-send-email-r.sricharan@ti.com> X-Mailer: git-send-email 1.7.1 MIME-Version: 1.0 Cc: trini@ti.com Subject: [U-Boot] [PATCH 1/5] ARM: cache: Move the cp15 CR register read before flushing the cache. X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de The following is the cleanup sequence in arch/arm/cpu/armv7/cpu.c int cleanup_before_linux(void) { ... ... dcache_disable(); v7_outer_cache_disable(); invalidate_dcache_all(); } 1) invalidate_dcache_all call expects that all the caches has been flushed, invalidated and there are no dirty entries prior to its execution. In the above sequence dcache_disable() flushes, invalidates the caches and turns off the mmu. But after it cleanups the cache and before the mmu is disabled there is a cp_delay() function which has STR instruction. On certain cores like the cortex-a15, cache hit and a write can happen to a cache line even when the dcache is disabled. So the above mentioned STR instruction creates a dirty entry after cleaning. The mmu gets disabled after this. 2) invalidate_dcache_all invalidates the cache lines. Again on cores like cortex-a15, invalidate instruction flushes the dirty line as well. So some times the dirty line from sequence 1 can corrupt the memory resulting in a crash. Fixing this by moving the get_cr() and cp_delay() calls before cleaning up the cache, thus avoiding the dirty entry. Signed-off-by: R Sricharan --- arch/arm/lib/cache-cp15.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index e6c3eae..939de10 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -115,17 +115,17 @@ static void cache_disable(uint32_t cache_bit) { uint32_t reg; + reg = get_cr(); + cp_delay(); + if (cache_bit == CR_C) { /* if cache isn;t enabled no need to disable */ - reg = get_cr(); if ((reg & CR_C) != CR_C) return; /* if disabling data cache, disable mmu too */ cache_bit |= CR_M; flush_dcache_all(); } - reg = get_cr(); - cp_delay(); set_cr(reg & ~cache_bit); } #endif