@@ -182,7 +182,7 @@ l2_disabled:
andi. r1,r3,L1CSR0_DCE@l
beq 2b
-#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB)
+#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL)
/*
* TLB entry for debuggging in AS1
* Create temporary TLB entry in AS0 to handle debug exception
@@ -1437,17 +1437,25 @@ relocate_code:
7: sync /* Wait for all icbi to complete on bus */
isync
- /*
- * Re-point the IVPR at RAM
- */
- mtspr IVPR,r10
-
/*
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
*/
addi r0,r10,in_ram - _start + _START_OFFSET
+
+#if defined(CONFIG_NAND_SPL)
+/*
+ * As IVPR is going to point RAM address,
+ * Make sure IVOR15 has valid opcode to support debugger
+ */
+ mtspr IVOR15,r0
+#endif
+ /*
+ * Re-point the IVPR at RAM
+ */
+ mtspr IVPR,r10
+
mtlr r0
blr /* NEVER RETURNS! */
.globl in_ram