From patchwork Wed Feb 15 13:57:31 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aneesh V X-Patchwork-Id: 141322 X-Patchwork-Delegate: albert.aribaud@free.fr Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id F2FB3B7001 for ; Thu, 16 Feb 2012 00:58:58 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3234E280E4; Wed, 15 Feb 2012 14:58:46 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 3c-ZaHYjqWnn; Wed, 15 Feb 2012 14:58:45 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5C2B2280E5; Wed, 15 Feb 2012 14:58:32 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 430F6280C0 for ; Wed, 15 Feb 2012 14:58:23 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id vdMJk3RAIpjx for ; Wed, 15 Feb 2012 14:58:22 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from na3sys009aog120.obsmtp.com (na3sys009aog120.obsmtp.com [74.125.149.140]) by theia.denx.de (Postfix) with ESMTPS id 227482809B for ; Wed, 15 Feb 2012 14:57:59 +0100 (CET) Received: from mail-tul01m020-f177.google.com ([209.85.214.177]) (using TLSv1) by na3sys009aob120.postini.com ([74.125.148.12]) with SMTP ID DSNKTzu55RfUlWszDRDL2as9Ifj8h+HJy1bT@postini.com; Wed, 15 Feb 2012 05:58:01 PST Received: by mail-tul01m020-f177.google.com with SMTP id uz6so2186594obc.22 for ; Wed, 15 Feb 2012 05:57:57 -0800 (PST) MIME-Version: 1.0 Received: by 10.182.162.40 with SMTP id xx8mr18770712obb.17.1329314277758; Wed, 15 Feb 2012 05:57:57 -0800 (PST) Received: from localhost (dragon.ti.com. [192.94.94.33]) by mx.google.com with ESMTPS id 1sm2997190obo.2.2012.02.15.05.57.54 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 15 Feb 2012 05:57:57 -0800 (PST) From: Aneesh V To: u-boot@lists.denx.de Date: Wed, 15 Feb 2012 19:27:31 +0530 Message-Id: <1329314253-4596-3-git-send-email-aneesh@ti.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1328528248-20872-1-git-send-email-aneesh@ti.com> References: <1328528248-20872-1-git-send-email-aneesh@ti.com> X-Gm-Message-State: ALoCoQn5+uUZlKpIh6jaevY42t+G24X5FeoEjuUDlyjhOyGXN9fUV3m3o3yNjMY6eA4+YW2J/ndn Subject: [U-Boot] [PATCH 2/4] arm: add %function attribute to assembly functions X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This is done using the following directive preceding each function definition: .type , %function This marks the symbol as a function in the object header which in turn helps the linker in some cases. In particular this was found needed for resolving ARM/Thumb calls correctly in a build with Thumb interworking enabled. This solves the following problem I had reported earlier: "When U-Boot/SPL is built using the Thumb instruction set the toolchain has a potential issue with weakly linked symbols. If a function has a weakly linked default implementation in C and a real implementation in assembly GCC is confused about the instruction set of the assembly implementation. As a result the assembly function that is built in ARM is executed as if it is Thumb. This results in a crash" Signed-off-by: Aneesh V --- Changes from RFC to V1: - This change completely replaces the previous workaround for the ARM/Thumb interwork problem, which was to wrap around the assembly function in question with a naked C function --- arch/arm/cpu/arm1136/omap24xx/reset.S | 3 +- arch/arm/cpu/arm1136/start.S | 7 +++- arch/arm/cpu/arm1176/s3c64xx/cpu_init.S | 3 +- arch/arm/cpu/arm1176/s3c64xx/reset.S | 3 +- arch/arm/cpu/arm1176/start.S | 9 +++-- arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S | 3 +- arch/arm/cpu/arm720t/lpc2292/iap_entry.S | 3 +- arch/arm/cpu/arm720t/start.S | 12 ++++-- arch/arm/cpu/arm920t/a320/reset.S | 1 + arch/arm/cpu/arm920t/at91/lowlevel_init.S | 3 +- arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S | 3 +- arch/arm/cpu/arm920t/ks8695/lowlevel_init.S | 3 +- arch/arm/cpu/arm920t/start.S | 6 ++- arch/arm/cpu/arm925t/start.S | 9 +++-- arch/arm/cpu/arm926ejs/at91/lowlevel_init.S | 4 +- arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S | 3 +- arch/arm/cpu/arm926ejs/davinci/reset.S | 3 +- arch/arm/cpu/arm926ejs/mx28/start.S | 3 +- arch/arm/cpu/arm926ejs/nomadik/reset.S | 3 +- arch/arm/cpu/arm926ejs/omap/reset.S | 3 +- arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S | 3 +- arch/arm/cpu/arm926ejs/start.S | 9 +++-- arch/arm/cpu/arm926ejs/versatile/reset.S | 3 +- arch/arm/cpu/arm946es/start.S | 9 +++-- arch/arm/cpu/arm_intcm/start.S | 15 ++------ arch/arm/cpu/armv7/mx5/lowlevel_init.S | 3 +- arch/arm/cpu/armv7/mx6/lowlevel_init.S | 3 +- arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 9 +++-- arch/arm/cpu/armv7/omap-common/reset.S | 1 + arch/arm/cpu/armv7/omap3/lowlevel_init.S | 45 ++++++++++++++++-------- arch/arm/cpu/armv7/s5pc1xx/cache.S | 2 + arch/arm/cpu/armv7/s5pc1xx/reset.S | 3 +- arch/arm/cpu/armv7/start.S | 9 +++-- arch/arm/cpu/armv7/tegra2/lowlevel_init.S | 1 + arch/arm/cpu/armv7/u8500/lowlevel.S | 6 ++- arch/arm/cpu/ixp/start.S | 9 +++-- arch/arm/cpu/lh7a40x/start.S | 9 +++-- arch/arm/cpu/pxa/start.S | 6 ++- arch/arm/cpu/s3c44b0/start.S | 6 ++- arch/arm/cpu/sa1100/start.S | 9 +++-- arch/arm/lib/_ashldi3.S | 6 ++- arch/arm/lib/_ashrdi3.S | 6 ++- arch/arm/lib/_divsi3.S | 6 ++- arch/arm/lib/_lshrdi3.S | 6 ++- arch/arm/lib/_modsi3.S | 3 +- arch/arm/lib/_udivsi3.S | 6 ++- arch/arm/lib/memcpy.S | 3 +- arch/arm/lib/memset.S | 3 +- 48 files changed, 186 insertions(+), 100 deletions(-) diff --git a/arch/arm/cpu/arm1136/omap24xx/reset.S b/arch/arm/cpu/arm1136/omap24xx/reset.S index 5f8343f..917a934 100644 --- a/arch/arm/cpu/arm1136/omap24xx/reset.S +++ b/arch/arm/cpu/arm1136/omap24xx/reset.S @@ -30,7 +30,8 @@ #include -.globl reset_cpu +.type reset_cpu, %function +.global reset_cpu reset_cpu: ldr r1, rstctl /* get addr for global reset reg */ mov r3, #0x2 /* full reset pll+mpu */ diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S index c0db96c..972fc0e 100644 --- a/arch/arm/cpu/arm1136/start.S +++ b/arch/arm/cpu/arm1136/start.S @@ -31,7 +31,8 @@ #include #include #include -.globl _start +.type _start, %function +.global _start _start: b reset #ifdef CONFIG_SPL_BUILD ldr pc, _hang @@ -178,7 +179,8 @@ call_board_init_f: * after relocating the monitor code. * */ - .globl relocate_code +.type relocate_code, %function +.global relocate_code relocate_code: mov r4, r0 /* save addr_sp */ mov r5, r1 /* save addr of gd */ @@ -510,6 +512,7 @@ fiq: #endif .align 5 +.type arm1136_cache_flush, %function .global arm1136_cache_flush arm1136_cache_flush: #if !defined(CONFIG_SYS_ICACHE_OFF) diff --git a/arch/arm/cpu/arm1176/s3c64xx/cpu_init.S b/arch/arm/cpu/arm1176/s3c64xx/cpu_init.S index df88cba..886a5ad 100644 --- a/arch/arm/cpu/arm1176/s3c64xx/cpu_init.S +++ b/arch/arm/cpu/arm1176/s3c64xx/cpu_init.S @@ -26,7 +26,8 @@ #include #include - .globl mem_ctrl_asm_init +.type mem_ctrl_asm_init, %function +.global mem_ctrl_asm_init mem_ctrl_asm_init: /* DMC1 base address 0x7e001000 */ ldr r0, =ELFIN_DMC1_BASE diff --git a/arch/arm/cpu/arm1176/s3c64xx/reset.S b/arch/arm/cpu/arm1176/s3c64xx/reset.S index eae572e..a33b063 100644 --- a/arch/arm/cpu/arm1176/s3c64xx/reset.S +++ b/arch/arm/cpu/arm1176/s3c64xx/reset.S @@ -23,7 +23,8 @@ #include -.globl reset_cpu +.type reset_cpu, %function +.global reset_cpu reset_cpu: ldr r1, =ELFIN_CLOCK_POWER_BASE ldr r2, [r1, #SYS_ID_OFFSET] diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index 848144a..e97a413 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -49,7 +49,8 @@ ************************************************************************* */ -.globl _start +.type _start, %function +.global _start _start: b reset #ifndef CONFIG_NAND_SPL ldr pc, _undefined_instruction @@ -240,7 +241,8 @@ call_board_init_f: * after relocating the monitor code. * */ - .globl relocate_code +.type relocate_code, %function +.global relocate_code relocate_code: mov r4, r0 /* save addr_sp */ mov r5, r1 /* save addr of gd */ @@ -406,7 +408,8 @@ _mmu_table_base: * void theLastJump(void *kernel, int arch_num, uint boot_params); */ #ifdef CONFIG_ENABLE_MMU - .globl theLastJump +.type theLastJump, %function +.global theLastJump theLastJump: mov r9, r0 ldr r3, =0xfff00000 diff --git a/arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S b/arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S index 3ee32ef..6d1e7e6 100644 --- a/arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S +++ b/arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S @@ -19,7 +19,8 @@ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ -.globl lowlevel_init +.type lowlevel_init, %function +.global lowlevel_init lowlevel_init: /* nothing for now, maybe needed for more exotic boot modes */ mov pc, lr diff --git a/arch/arm/cpu/arm720t/lpc2292/iap_entry.S b/arch/arm/cpu/arm720t/lpc2292/iap_entry.S index c31d519..a944c35 100644 --- a/arch/arm/cpu/arm720t/lpc2292/iap_entry.S +++ b/arch/arm/cpu/arm720t/lpc2292/iap_entry.S @@ -1,6 +1,7 @@ IAP_ADDRESS: .word 0x7FFFFFF1 -.globl iap_entry +.type iap_entry, %function +.global iap_entry iap_entry: ldr r2, IAP_ADDRESS bx r2 diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index 540e3c2..e34a8bc 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -37,7 +37,8 @@ */ -.globl _start +.type _start, %function +.global _start _start: b reset ldr pc, _undefined_instruction ldr pc, _software_interrupt @@ -155,7 +156,8 @@ call_board_init_f: * after relocating the monitor code. * */ - .globl relocate_code +.type relocate_code, %function +.global relocate_code relocate_code: mov r4, r0 /* save addr_sp */ mov r5, r1 /* save addr of gd */ @@ -590,7 +592,8 @@ fiq: #if defined(CONFIG_NETARM) .align 5 -.globl reset_cpu +.type reset_cpu, %function +.global reset_cpu reset_cpu: ldr r1, =NETARM_MEM_MODULE_BASE ldr r0, [r1, #+NETARM_MEM_CS0_BASE_ADDR] @@ -615,7 +618,8 @@ reset_cpu: /* No specific reset actions for IntegratorAP/CM720T as yet */ #elif defined(CONFIG_LPC2292) .align 5 -.globl reset_cpu +.type reset_cpu, %function +.global reset_cpu reset_cpu: mov pc, r0 #else diff --git a/arch/arm/cpu/arm920t/a320/reset.S b/arch/arm/cpu/arm920t/a320/reset.S index 12ca527..6c83245 100644 --- a/arch/arm/cpu/arm920t/a320/reset.S +++ b/arch/arm/cpu/arm920t/a320/reset.S @@ -17,6 +17,7 @@ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ +.type reset_cpu, %function .global reset_cpu reset_cpu: b reset_cpu diff --git a/arch/arm/cpu/arm920t/at91/lowlevel_init.S b/arch/arm/cpu/arm920t/at91/lowlevel_init.S index 8b58ba9..ea7676a 100644 --- a/arch/arm/cpu/arm920t/at91/lowlevel_init.S +++ b/arch/arm/cpu/arm920t/at91/lowlevel_init.S @@ -44,7 +44,8 @@ _MTEXT_BASE: .word CONFIG_SYS_TEXT_BASE #endif -.globl lowlevel_init +.type lowlevel_init, %function +.global lowlevel_init lowlevel_init: ldr r1, =AT91_ASM_PMC_MOR /* Main oscillator Enable register */ diff --git a/arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S b/arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S index f21e237..b038298 100644 --- a/arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S +++ b/arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S @@ -27,7 +27,8 @@ #include #include -.globl lowlevel_init +.type lowlevel_init, %function +.global lowlevel_init lowlevel_init: /* backup return address */ ldr r1, =SYSCON_SCRATCH0 diff --git a/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S b/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S index e9f1227..b3f6c3e 100644 --- a/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S +++ b/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S @@ -64,7 +64,8 @@ ************************************************************************* */ -.globl lowlevel_init +.type lowlevel_init, %function +.global lowlevel_init lowlevel_init: #if DEBUG diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S index 8c5612c..43b9e3c 100644 --- a/arch/arm/cpu/arm920t/start.S +++ b/arch/arm/cpu/arm920t/start.S @@ -37,7 +37,8 @@ */ -.globl _start +.type _start, %function +.global _start _start: b start_code ldr pc, _undefined_instruction ldr pc, _software_interrupt @@ -198,7 +199,8 @@ call_board_init_f: * after relocating the monitor code. * */ - .globl relocate_code +.type relocate_code, %function +.global relocate_code relocate_code: mov r4, r0 /* save addr_sp */ mov r5, r1 /* save addr of gd */ diff --git a/arch/arm/cpu/arm925t/start.S b/arch/arm/cpu/arm925t/start.S index dbb93ef..de277e6 100644 --- a/arch/arm/cpu/arm925t/start.S +++ b/arch/arm/cpu/arm925t/start.S @@ -47,7 +47,8 @@ */ -.globl _start +.type _start, %function +.global _start _start: b reset ldr pc, _undefined_instruction ldr pc, _software_interrupt @@ -192,7 +193,8 @@ call_board_init_f: * after relocating the monitor code. * */ - .globl relocate_code +.type relocate_code, %function +.global relocate_code relocate_code: mov r4, r0 /* save addr_sp */ mov r5, r1 /* save addr of gd */ @@ -507,7 +509,8 @@ fiq: #endif .align 5 -.globl reset_cpu +.type reset_cpu, %function +.global reset_cpu reset_cpu: ldr r1, rstctl1 /* get clkm1 reset ctl */ mov r3, #0x3 /* dsp_en + arm_rst = global reset */ diff --git a/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S b/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S index d102195..f946977 100644 --- a/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S +++ b/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S @@ -45,8 +45,8 @@ _TEXT_BASE: .word CONFIG_SYS_TEXT_BASE -.globl lowlevel_init -.type lowlevel_init,function +.type lowlevel_init, %function +.global lowlevel_init lowlevel_init: mov r5, pc /* r5 = POS1 + 4 current */ diff --git a/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S b/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S index 7a169b1..4161e93 100644 --- a/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S +++ b/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S @@ -47,7 +47,8 @@ #define MDSTAT_STATE 0x3f -.globl lowlevel_init +.type lowlevel_init, %function +.global lowlevel_init lowlevel_init: /*-------------------------------------------------------* diff --git a/arch/arm/cpu/arm926ejs/davinci/reset.S b/arch/arm/cpu/arm926ejs/davinci/reset.S index ba0a7c3..8dbb2fa 100644 --- a/arch/arm/cpu/arm926ejs/davinci/reset.S +++ b/arch/arm/cpu/arm926ejs/davinci/reset.S @@ -21,7 +21,8 @@ * MA 02111-1307 USA */ -.globl reset_cpu +.type reset_cpu, %function +.global reset_cpu reset_cpu: ldr r0, WDT_TGCR mov r1, $0x08 diff --git a/arch/arm/cpu/arm926ejs/mx28/start.S b/arch/arm/cpu/arm926ejs/mx28/start.S index 2cd4d73..a284b4c 100644 --- a/arch/arm/cpu/arm926ejs/mx28/start.S +++ b/arch/arm/cpu/arm926ejs/mx28/start.S @@ -49,7 +49,8 @@ */ -.globl _start +.type _start, %function +.global _start _start: b reset b undefined_instruction diff --git a/arch/arm/cpu/arm926ejs/nomadik/reset.S b/arch/arm/cpu/arm926ejs/nomadik/reset.S index ec95472..184c066 100644 --- a/arch/arm/cpu/arm926ejs/nomadik/reset.S +++ b/arch/arm/cpu/arm926ejs/nomadik/reset.S @@ -4,7 +4,8 @@ */ .align 5 -.globl reset_cpu +.type reset_cpu, %function +.global reset_cpu reset_cpu: ldr r0, =NOMADIK_SRC_BASE /* System and Reset Controller */ ldr r1, =0x1 diff --git a/arch/arm/cpu/arm926ejs/omap/reset.S b/arch/arm/cpu/arm926ejs/omap/reset.S index 8321072..3e729a4 100644 --- a/arch/arm/cpu/arm926ejs/omap/reset.S +++ b/arch/arm/cpu/arm926ejs/omap/reset.S @@ -31,7 +31,8 @@ */ .align 5 -.globl reset_cpu +.type reset_cpu, %function +.global reset_cpu reset_cpu: ldr r1, rstctl1 /* get clkm1 reset ctl */ mov r3, #0x0 diff --git a/arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S b/arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S index a2de3cf..4e17a38 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S +++ b/arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S @@ -82,7 +82,8 @@ * up RAM for us to relocate into. */ -.globl lowlevel_init +.type lowlevel_init, %function +.global lowlevel_init lowlevel_init: diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index 6a09c02..928c36d 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -52,14 +52,16 @@ #ifdef CONFIG_SYS_DV_NOR_BOOT_CFG -.globl _start +.type _start, %function +.global _start _start: .globl _NOR_BOOT_CFG _NOR_BOOT_CFG: .word CONFIG_SYS_DV_NOR_BOOT_CFG b reset #else -.globl _start +.type _start, %function +.global _start _start: b reset #endif @@ -220,7 +222,8 @@ call_board_init_f: * after relocating the monitor code. * */ - .globl relocate_code +.type relocate_code, %function +.global relocate_code relocate_code: mov r4, r0 /* save addr_sp */ mov r5, r1 /* save addr of gd */ diff --git a/arch/arm/cpu/arm926ejs/versatile/reset.S b/arch/arm/cpu/arm926ejs/versatile/reset.S index 8321072..3e729a4 100644 --- a/arch/arm/cpu/arm926ejs/versatile/reset.S +++ b/arch/arm/cpu/arm926ejs/versatile/reset.S @@ -31,7 +31,8 @@ */ .align 5 -.globl reset_cpu +.type reset_cpu, %function +.global reset_cpu reset_cpu: ldr r1, rstctl1 /* get clkm1 reset ctl */ mov r3, #0x0 diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S index 89ba558..7a6f81a 100644 --- a/arch/arm/cpu/arm946es/start.S +++ b/arch/arm/cpu/arm946es/start.S @@ -44,7 +44,8 @@ */ -.globl _start +.type _start, %function +.global _start _start: b reset ldr pc, _undefined_instruction @@ -163,7 +164,8 @@ call_board_init_f: * after relocating the monitor code. * */ - .globl relocate_code +.type relocate_code, %function +.global relocate_code relocate_code: mov r4, r0 /* save addr_sp */ mov r5, r1 /* save addr of gd */ @@ -482,7 +484,8 @@ fiq: #else .align 5 -.globl reset_cpu +.type reset_cpu, %function +.global reset_cpu reset_cpu: ldr r1, rstctl1 /* get clkm1 reset ctl */ diff --git a/arch/arm/cpu/arm_intcm/start.S b/arch/arm/cpu/arm_intcm/start.S index 2033b36..ff7f040 100644 --- a/arch/arm/cpu/arm_intcm/start.S +++ b/arch/arm/cpu/arm_intcm/start.S @@ -42,7 +42,8 @@ ************************************************************************* */ -.globl _start +.type _start, %function +.global _start _start: b reset ldr pc, _undefined_instruction @@ -159,7 +160,8 @@ call_board_init_f: * after relocating the monitor code. * */ - .globl relocate_code +.type relocate_code, %function +.global relocate_code relocate_code: mov r4, r0 /* save addr_sp */ mov r5, r1 /* save addr of gd */ @@ -393,35 +395,30 @@ cpu_init_crit: * exception handlers */ .align 5 -.globl undefined_instruction undefined_instruction: get_bad_stack bad_save_user_regs bl do_undefined_instruction .align 5 -.globl software_interrupt software_interrupt: get_bad_stack bad_save_user_regs bl do_software_interrupt .align 5 -.globl prefetch_abort prefetch_abort: get_bad_stack bad_save_user_regs bl do_prefetch_abort .align 5 -.globl data_abort data_abort: get_bad_stack bad_save_user_regs bl do_data_abort .align 5 -.globl not_used not_used: get_bad_stack bad_save_user_regs @@ -429,7 +426,6 @@ not_used: #ifdef CONFIG_USE_IRQ .align 5 -.globl irq irq: get_irq_stack irq_save_user_regs @@ -437,7 +433,6 @@ irq: irq_restore_user_regs .align 5 -.globl fiq fiq: get_fiq_stack /* someone ought to write a more effiction fiq_save_user_regs */ @@ -448,14 +443,12 @@ fiq: #else .align 5 -.globl irq irq: get_bad_stack bad_save_user_regs bl do_irq .align 5 -.globl fiq fiq: get_bad_stack bad_save_user_regs diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S index 01f6d75..debe038 100644 --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -312,7 +312,8 @@ .section ".text.init", "x" -.globl lowlevel_init +.type lowlevel_init, %function +.global lowlevel_init lowlevel_init: #if defined(CONFIG_MX51) ldr r0, =GPIO1_BASE_ADDR diff --git a/arch/arm/cpu/armv7/mx6/lowlevel_init.S b/arch/arm/cpu/armv7/mx6/lowlevel_init.S index 1864356..b551711 100644 --- a/arch/arm/cpu/armv7/mx6/lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx6/lowlevel_init.S @@ -18,7 +18,8 @@ */ .section ".text.init", "x" -.globl lowlevel_init +.type lowlevel_init, %function +.global lowlevel_init lowlevel_init: mov pc, lr diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S index 35f38ac..1c8edf3 100644 --- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S @@ -28,7 +28,8 @@ #include -.global save_boot_params +.type save_boot_params, %function +.global save_boot_params save_boot_params: /* * See if the rom code passed pointer is valid: @@ -78,7 +79,8 @@ save_boot_params: bx lr -.globl lowlevel_init +.type lowlevel_init, %function +.global lowlevel_init lowlevel_init: /* * Setup a temporary stack @@ -96,7 +98,8 @@ lowlevel_init: bl s_init pop {ip, pc} -.globl set_pl310_ctrl_reg +.type set_pl310_ctrl_reg, %function +.global set_pl310_ctrl_reg set_pl310_ctrl_reg: PUSH {r4-r11, lr} @ save registers - ROM code may pollute @ our registers diff --git a/arch/arm/cpu/armv7/omap-common/reset.S b/arch/arm/cpu/armv7/omap-common/reset.S index 838b122..3697170 100644 --- a/arch/arm/cpu/armv7/omap-common/reset.S +++ b/arch/arm/cpu/armv7/omap-common/reset.S @@ -23,6 +23,7 @@ #include +.type reset_cpu, %function .global reset_cpu reset_cpu: ldr r1, rstctl @ get addr for global reset diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S index 2f6930b..05aac7b 100644 --- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S @@ -35,7 +35,8 @@ _TEXT_BASE: .word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */ -.global save_boot_params +.type save_boot_params, %function +.global save_boot_params save_boot_params: #ifdef CONFIG_SPL_BUILD ldr r4, =omap3_boot_device @@ -45,7 +46,8 @@ save_boot_params: #endif bx lr -.global omap3_gp_romcode_call +.type omap3_gp_romcode_call, %function +.global omap3_gp_romcode_call omap3_gp_romcode_call: PUSH {r4-r12, lr} @ Save all registers from ROM code! MOV r12, r0 @ Copy the Service ID in R12 @@ -62,7 +64,8 @@ omap3_gp_romcode_call: * R0 - Service ID * R1 - paramer list */ -.global do_omap3_emu_romcode_call +.type do_omap3_emu_romcode_call, %function +.global do_omap3_emu_romcode_call do_omap3_emu_romcode_call: PUSH {r4-r12, lr} @ Save all registers from ROM code! MOV r12, r0 @ Copy the Secure Service ID in R12 @@ -82,7 +85,8 @@ do_omap3_emu_romcode_call: * cpy_clk_code: relocates clock code into SRAM where its safer to execute * R1 = SRAM destination address. *************************************************************************/ -.global cpy_clk_code +.type cpy_clk_code, %function +.global cpy_clk_code cpy_clk_code: /* Copy DPLL code into SRAM */ adr r0, go_to_speed /* get addr of clock setting code */ @@ -109,7 +113,8 @@ next2: * L3 when its not in self refresh seems bad for it. Normally, this * code runs from flash before SDR is init so that should be ok. ****************************************************************************/ -.global go_to_speed +.type go_to_speed, %function +.global go_to_speed go_to_speed: stmfd sp!, {r4 - r6} @@ -211,7 +216,8 @@ pll_div_val5: #endif -.globl lowlevel_init +.type lowlevel_init, %function +.global lowlevel_init lowlevel_init: ldr sp, SRAM_STACK str ip, [sp] /* stash old link register */ @@ -289,7 +295,8 @@ mpu_dpll_param: .word MPU_M_38P4, MPU_N_38P4, MPU_FSEL_38P4, MPU_M2_38P4 -.globl get_mpu_dpll_param +.type get_mpu_dpll_param, %function +.global get_mpu_dpll_param get_mpu_dpll_param: adr r0, mpu_dpll_param mov pc, lr @@ -336,7 +343,8 @@ iva_dpll_param: .word IVA_M_38P4, IVA_N_38P4, IVA_FSEL_38P4, IVA_M2_38P4 -.globl get_iva_dpll_param +.type get_iva_dpll_param, %function +.global get_iva_dpll_param get_iva_dpll_param: adr r0, iva_dpll_param mov pc, lr @@ -383,7 +391,8 @@ core_dpll_param: /* 3410 */ .word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4 -.globl get_core_dpll_param +.type get_core_dpll_param, %function +.global get_core_dpll_param get_core_dpll_param: adr r0, core_dpll_param mov pc, lr @@ -405,7 +414,8 @@ per_dpll_param: /* 38.4MHz */ .word PER_M_38P4, PER_N_38P4, PER_FSEL_38P4, PER_M2_38P4 -.globl get_per_dpll_param +.type get_per_dpll_param, %function +.global get_per_dpll_param get_per_dpll_param: adr r0, per_dpll_param mov pc, lr @@ -427,7 +437,8 @@ per2_dpll_param: /* 38.4MHz */ .word PER2_M_38P4, PER2_N_38P4, PER2_FSEL_38P4, PER2_M2_38P4 -.globl get_per2_dpll_param +.type get_per2_dpll_param, %function +.global get_per2_dpll_param get_per2_dpll_param: adr r0, per2_dpll_param mov pc, lr @@ -480,22 +491,26 @@ per_36x_dpll_param: .word 26000, 432, 12, 9, 16, 9, 4, 3, 1 .word 38400, 360, 15, 9, 16, 5, 4, 3, 1 -.globl get_36x_mpu_dpll_param +.type get_36x_mpu_dpll_param, %function +.global get_36x_mpu_dpll_param get_36x_mpu_dpll_param: adr r0, mpu_36x_dpll_param mov pc, lr -.globl get_36x_iva_dpll_param +.type get_36x_iva_dpll_param, %function +.global get_36x_iva_dpll_param get_36x_iva_dpll_param: adr r0, iva_36x_dpll_param mov pc, lr -.globl get_36x_core_dpll_param +.type get_36x_core_dpll_param, %function +.global get_36x_core_dpll_param get_36x_core_dpll_param: adr r0, core_36x_dpll_param mov pc, lr -.globl get_36x_per_dpll_param +.type get_36x_per_dpll_param, %function +.global get_36x_per_dpll_param get_36x_per_dpll_param: adr r0, per_36x_dpll_param mov pc, lr diff --git a/arch/arm/cpu/armv7/s5pc1xx/cache.S b/arch/arm/cpu/armv7/s5pc1xx/cache.S index c7d6221..1f47203 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/cache.S +++ b/arch/arm/cpu/armv7/s5pc1xx/cache.S @@ -26,6 +26,7 @@ .align 5 #ifndef CONFIG_SYS_L2CACHE_OFF +.type v7_outer_cache_enable, %function .global v7_outer_cache_enable v7_outer_cache_enable: push {r0, r1, r2, lr} @@ -34,6 +35,7 @@ v7_outer_cache_enable: mcr 15, 0, r3, cr1, cr0, 1 pop {r1, r2, r3, pc} +.type v7_outer_cache_disable, %function .global v7_outer_cache_disable v7_outer_cache_disable: push {r0, r1, r2, lr} diff --git a/arch/arm/cpu/armv7/s5pc1xx/reset.S b/arch/arm/cpu/armv7/s5pc1xx/reset.S index 70fa146..65e197e 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/reset.S +++ b/arch/arm/cpu/armv7/s5pc1xx/reset.S @@ -26,7 +26,8 @@ #define S5PC100_SWRESET 0xE0200000 #define S5PC110_SWRESET 0xE0102000 -.globl reset_cpu +.type reset_cpu, %function +.global reset_cpu reset_cpu: ldr r1, =S5PC100_PRO_ID ldr r2, [r1] diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index ef08a55..5679365 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -34,7 +34,8 @@ #include #include -.globl _start +.type _start, %function +.global _start _start: b reset ldr pc, _undefined_instruction ldr pc, _software_interrupt @@ -172,7 +173,8 @@ call_board_init_f: * after relocating the monitor code. * */ - .globl relocate_code +.type relocate_code, %function +.global relocate_code relocate_code: mov r4, r0 /* save addr_sp */ mov r5, r1 /* save addr of gd */ @@ -298,7 +300,8 @@ _board_init_r_ofs: * CONFIG_SYS_ICACHE_OFF is defined. * *************************************************************************/ -.globl cpu_init_cp15 +.type cpu_init_cp15, %function +.global cpu_init_cp15 cpu_init_cp15: /* * Invalidate L1 I/D diff --git a/arch/arm/cpu/armv7/tegra2/lowlevel_init.S b/arch/arm/cpu/armv7/tegra2/lowlevel_init.S index 6b86647..f4a8cb0 100644 --- a/arch/arm/cpu/armv7/tegra2/lowlevel_init.S +++ b/arch/arm/cpu/armv7/tegra2/lowlevel_init.S @@ -27,6 +27,7 @@ #include .align 5 +.type reset_cpu, %function .global reset_cpu reset_cpu: ldr r1, rstctl @ get addr for global reset diff --git a/arch/arm/cpu/armv7/u8500/lowlevel.S b/arch/arm/cpu/armv7/u8500/lowlevel.S index cffdfd1..66ecd93 100644 --- a/arch/arm/cpu/armv7/u8500/lowlevel.S +++ b/arch/arm/cpu/armv7/u8500/lowlevel.S @@ -21,12 +21,14 @@ #include -.globl lowlevel_init +.type lowlevel_init, %function +.global lowlevel_init lowlevel_init: mov pc, lr .align 5 -.globl reset_cpu +.type reset_cpu, %function +.global reset_cpu reset_cpu: ldr r0, =CFG_PRCMU_BASE ldr r1, =0x1 diff --git a/arch/arm/cpu/ixp/start.S b/arch/arm/cpu/ixp/start.S index cb32121..bc35566 100644 --- a/arch/arm/cpu/ixp/start.S +++ b/arch/arm/cpu/ixp/start.S @@ -64,7 +64,8 @@ sub pc,pc,#4 .endm -.globl _start +.type _start, %function +.global _start _start: ldr pc, _reset ldr pc, _undefined_instruction @@ -261,7 +262,8 @@ call_board_init_f: * after relocating the monitor code. * */ - .globl relocate_code +.type relocate_code, %function +.global relocate_code relocate_code: mov r4, r0 /* save addr_sp */ mov r5, r1 /* save addr of gd */ @@ -537,7 +539,8 @@ fiq: /****************************************************************************/ .align 5 -.globl reset_cpu +.type reset_cpu, %function +.global reset_cpu reset_cpu: ldr r1, =0x482e diff --git a/arch/arm/cpu/lh7a40x/start.S b/arch/arm/cpu/lh7a40x/start.S index 62de8b8..585fcaf 100644 --- a/arch/arm/cpu/lh7a40x/start.S +++ b/arch/arm/cpu/lh7a40x/start.S @@ -37,7 +37,8 @@ */ -.globl _start +.type _start, %function +.global _start _start: b reset ldr pc, _undefined_instruction ldr pc, _software_interrupt @@ -172,7 +173,8 @@ call_board_init_f: * after relocating the monitor code. * */ - .globl relocate_code +.type relocate_code, %function +.global relocate_code relocate_code: mov r4, r0 /* save addr_sp */ mov r5, r1 /* save addr of gd */ @@ -482,7 +484,8 @@ fiq: #endif .align 5 -.globl reset_cpu +.type reset_cpu, %function +.global reset_cpu reset_cpu: bl disable_interrupts diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S index ba0de8f..a07ef19 100644 --- a/arch/arm/cpu/pxa/start.S +++ b/arch/arm/cpu/pxa/start.S @@ -45,7 +45,8 @@ #endif #endif -.globl _start +.type _start, %function +.global _start _start: b reset #ifdef CONFIG_SPL_BUILD ldr pc, _hang @@ -180,7 +181,8 @@ call_board_init_f: * after relocating the monitor code. * */ - .globl relocate_code +.type relocate_code, %function +.global relocate_code relocate_code: mov r4, r0 /* save addr_sp */ mov r5, r1 /* save addr of gd */ diff --git a/arch/arm/cpu/s3c44b0/start.S b/arch/arm/cpu/s3c44b0/start.S index a29d5b4..ac1e1b1 100644 --- a/arch/arm/cpu/s3c44b0/start.S +++ b/arch/arm/cpu/s3c44b0/start.S @@ -36,7 +36,8 @@ */ -.globl _start +.type _start, %function +.global _start _start: b reset add pc, pc, #0x0c000000 add pc, pc, #0x0c000000 @@ -144,7 +145,8 @@ call_board_init_f: * after relocating the monitor code. * */ - .globl relocate_code +.type relocate_code, %function +.global relocate_code relocate_code: mov r4, r0 /* save addr_sp */ mov r5, r1 /* save addr of gd */ diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S index 92546d8..4e77c8e 100644 --- a/arch/arm/cpu/sa1100/start.S +++ b/arch/arm/cpu/sa1100/start.S @@ -38,7 +38,8 @@ */ -.globl _start +.type _start, %function +.global _start _start: b reset ldr pc, _undefined_instruction ldr pc, _software_interrupt @@ -148,7 +149,8 @@ call_board_init_f: * after relocating the monitor code. * */ - .globl relocate_code +.type relocate_code, %function +.global relocate_code relocate_code: mov r4, r0 /* save addr_sp */ mov r5, r1 /* save addr of gd */ @@ -487,7 +489,8 @@ fiq: #endif .align 5 -.globl reset_cpu +.type reset_cpu, %function +.global reset_cpu reset_cpu: ldr r0, RST_BASE mov r1, #0x0 @ set bit 3-0 ... diff --git a/arch/arm/lib/_ashldi3.S b/arch/arm/lib/_ashldi3.S index 834ddc2..248c612 100644 --- a/arch/arm/lib/_ashldi3.S +++ b/arch/arm/lib/_ashldi3.S @@ -34,8 +34,10 @@ Boston, MA 02110-1301, USA. */ #define ah r1 #endif -.globl __ashldi3 -.globl __aeabi_llsl +.type __ashldi3, %function +.global __ashldi3 +.type __aeabi_llsl, %function +.global __aeabi_llsl __ashldi3: __aeabi_llsl: diff --git a/arch/arm/lib/_ashrdi3.S b/arch/arm/lib/_ashrdi3.S index 671ac87..f070f59 100644 --- a/arch/arm/lib/_ashrdi3.S +++ b/arch/arm/lib/_ashrdi3.S @@ -34,8 +34,10 @@ Boston, MA 02110-1301, USA. */ #define ah r1 #endif -.globl __ashrdi3 -.globl __aeabi_lasr +.type __ashrdi3, %function +.global __ashrdi3 +.type __aeabi_lasr, %function +.global __aeabi_lasr __ashrdi3: __aeabi_lasr: diff --git a/arch/arm/lib/_divsi3.S b/arch/arm/lib/_divsi3.S index cfbadb2..9e76909 100644 --- a/arch/arm/lib/_divsi3.S +++ b/arch/arm/lib/_divsi3.S @@ -95,8 +95,10 @@ .endm .align 5 -.globl __divsi3 -.globl __aeabi_idiv +.type __divsi3, %function +.global __divsi3 +.type __aeabi_idiv, %function +.global __aeabi_idiv __divsi3: __aeabi_idiv: cmp r1, #0 diff --git a/arch/arm/lib/_lshrdi3.S b/arch/arm/lib/_lshrdi3.S index e7fa799..0df05c2 100644 --- a/arch/arm/lib/_lshrdi3.S +++ b/arch/arm/lib/_lshrdi3.S @@ -34,8 +34,10 @@ Boston, MA 02110-1301, USA. */ #define ah r1 #endif -.globl __lshrdi3 -.globl __aeabi_llsr +.type __lshrdi3, %function +.global __lshrdi3 +.type __aeabi_llsr, %function +.global __aeabi_llsr __lshrdi3: __aeabi_llsr: diff --git a/arch/arm/lib/_modsi3.S b/arch/arm/lib/_modsi3.S index 539c584..bc07f49 100644 --- a/arch/arm/lib/_modsi3.S +++ b/arch/arm/lib/_modsi3.S @@ -70,7 +70,8 @@ .endm .align 5 -.globl __modsi3 +.type __modsi3, %function +.global __modsi3 __modsi3: cmp r1, #0 beq Ldiv0 diff --git a/arch/arm/lib/_udivsi3.S b/arch/arm/lib/_udivsi3.S index 1309802..e38d1d8 100644 --- a/arch/arm/lib/_udivsi3.S +++ b/arch/arm/lib/_udivsi3.S @@ -72,7 +72,8 @@ Ldiv0: ldmia sp!, {pc} .size __udivsi3 , . - __udivsi3 -.globl __aeabi_uidivmod +.type __aeabi_uidivmod, %function +.global __aeabi_uidivmod __aeabi_uidivmod: stmfd sp!, {r0, r1, ip, lr} @@ -82,7 +83,8 @@ __aeabi_uidivmod: sub r1, r1, r3 mov pc, lr -.globl __aeabi_idivmod +.type __aeabi_idivmod, %function +.global __aeabi_idivmod __aeabi_idivmod: stmfd sp!, {r0, r1, ip, lr} diff --git a/arch/arm/lib/memcpy.S b/arch/arm/lib/memcpy.S index f655256..313f82a 100644 --- a/arch/arm/lib/memcpy.S +++ b/arch/arm/lib/memcpy.S @@ -57,7 +57,8 @@ /* Prototype: void *memcpy(void *dest, const void *src, size_t n); */ -.globl memcpy +.type memcpy, %function +.global memcpy memcpy: cmp r0, r1 diff --git a/arch/arm/lib/memset.S b/arch/arm/lib/memset.S index 0cdf895..5f80539 100644 --- a/arch/arm/lib/memset.S +++ b/arch/arm/lib/memset.S @@ -27,7 +27,8 @@ * memset again. */ -.globl memset +.type memset, %function +.global memset memset: ands r3, r0, #3 @ 1 unaligned? bne 1b @ 1