From patchwork Sun Jan 29 18:59:49 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Nelson X-Patchwork-Id: 138468 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 641BB1007D1 for ; Mon, 30 Jan 2012 06:17:51 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1A41B28099; Sun, 29 Jan 2012 20:17:40 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id cvcoyDsKyJxi; Sun, 29 Jan 2012 20:17:39 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CAD3D280BE; Sun, 29 Jan 2012 20:17:13 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CDCBC280A8 for ; Sun, 29 Jan 2012 20:17:09 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id MdbXDWf4FlcL for ; Sun, 29 Jan 2012 20:17:09 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from fed1rmfepi102.cox.net (fed1rmfepi102.cox.net [68.230.241.133]) by theia.denx.de (Postfix) with ESMTP id 3CEDC280A9 for ; Sun, 29 Jan 2012 20:16:55 +0100 (CET) Received: from fed1rmimpo110.cox.net ([68.230.241.159]) by fed1rmfepo103.cox.net (InterMail vM.8.01.04.00 201-2260-137-20101110) with ESMTP id <20120129190001.QHUH3801.fed1rmfepo103.cox.net@fed1rmimpo110.cox.net>; Sun, 29 Jan 2012 14:00:01 -0500 Received: from ericsony.localdomain6 ([68.230.116.166]) by fed1rmimpo110.cox.net with bizsmtp id TX001i0033bV49g03X016g; Sun, 29 Jan 2012 14:00:01 -0500 X-CT-Class: Clean X-CT-Score: 0.00 X-CT-RefID: str=0001.0A020207.4F259731.0070,ss=1,re=0.000,fgs=0 X-CT-Spam: 0 X-Authority-Analysis: v=1.1 cv=5RePncF+00wnRIuVW5OoqKytqzC3r8jLIdEm+Wz8FvA= c=1 sm=1 a=pPC3xd24RR4A:10 a=rcTfVT_afHIA:10 a=zukJ/Oo2bNzQHA4rRbcyFw==:17 a=R_N1NMmAAAAA:8 a=hVcwujEvAAAA:8 a=Rvn42br9hx_MtCkuj6EA:9 a=QOiTB_lUNkwA:10 a=-Pj1cSz79GQA:10 a=zukJ/Oo2bNzQHA4rRbcyFw==:117 X-CM-Score: 0.00 Authentication-Results: cox.net; none From: Eric Nelson To: u-boot@lists.denx.de Date: Sun, 29 Jan 2012 11:59:49 -0700 Message-Id: <1327863595-1524-3-git-send-email-eric.nelson@boundarydevices.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1327863595-1524-1-git-send-email-eric.nelson@boundarydevices.com> References: <1327863595-1524-1-git-send-email-eric.nelson@boundarydevices.com> Cc: dirk.behme@de.bosch.com, matthias.fuchs@esd.eu, jason.hui@linaro.org Subject: [U-Boot] [PATCH V4 2/7] mx6q: Add support for ECSPI through mxc_spi driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Signed-off-by: Eric Nelson Acked-by: Dirk Behme Acked-by: Stefano Babic --- arch/arm/include/asm/arch-mx6/imx-regs.h | 44 ++++++++++++++++++++++++++++++ 1 files changed, 44 insertions(+), 0 deletions(-) diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 7650cb9..00040c4 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -190,6 +190,50 @@ struct src { u32 gpr10; }; +/* ECSPI registers */ +struct cspi_regs { + u32 rxdata; + u32 txdata; + u32 ctrl; + u32 cfg; + u32 intr; + u32 dma; + u32 stat; + u32 period; +}; + +/* + * CSPI register definitions + */ +#define MXC_ECSPI +#define MXC_CSPICTRL_EN (1 << 0) +#define MXC_CSPICTRL_MODE (1 << 1) +#define MXC_CSPICTRL_XCH (1 << 2) +#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) +#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) +#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) +#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) +#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) +#define MXC_CSPICTRL_MAXBITS 0xfff +#define MXC_CSPICTRL_TC (1 << 7) +#define MXC_CSPICTRL_RXOVF (1 << 6) +#define MXC_CSPIPERIOD_32KHZ (1 << 15) +#define MAX_SPI_BYTES 32 + +/* Bit position inside CTRL register to be associated with SS */ +#define MXC_CSPICTRL_CHAN 18 + +/* Bit position inside CON register to be associated with SS */ +#define MXC_CSPICON_POL 4 +#define MXC_CSPICON_PHA 0 +#define MXC_CSPICON_SSPOL 12 +#define MXC_SPI_BASE_ADDRESSES \ + ECSPI1_BASE_ADDR, \ + ECSPI2_BASE_ADDR, \ + ECSPI3_BASE_ADDR, \ + ECSPI4_BASE_ADDR, \ + ECSPI5_BASE_ADDR + struct iim_regs { u32 ctrl; u32 ctrl_set;