From patchwork Sun Jan 8 09:24:47 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Frysinger X-Patchwork-Id: 134895 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id A39B0B6F68 for ; Sun, 8 Jan 2012 20:24:55 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BBB2228374; Sun, 8 Jan 2012 10:24:53 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 9l1VxcU84cee; Sun, 8 Jan 2012 10:24:53 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0A7AA2837A; Sun, 8 Jan 2012 10:24:51 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1FA6A2837A for ; Sun, 8 Jan 2012 10:24:49 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id b1gj59ENFoBF for ; Sun, 8 Jan 2012 10:24:48 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from smtp.gentoo.org (smtp.gentoo.org [140.211.166.183]) by theia.denx.de (Postfix) with ESMTPS id A896628374 for ; Sun, 8 Jan 2012 10:24:46 +0100 (CET) Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.gentoo.org (Postfix) with ESMTP id 2DD7F1B400C; Sun, 8 Jan 2012 09:24:44 +0000 (UTC) From: Mike Frysinger To: u-boot@lists.denx.de Date: Sun, 8 Jan 2012 04:24:47 -0500 Message-Id: <1326014687-15831-1-git-send-email-vapier@gentoo.org> X-Mailer: git-send-email 1.7.8.3 In-Reply-To: <014501cca57b$1d65e800$2901a8c0@dpn> References: <014501cca57b$1d65e800$2901a8c0@dpn> Subject: [U-Boot] [PATCH v2] Blackfin: pr1: new board port X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Dimitar Penev This add support for the PR1 Appliance - Asterisk based ISDN PRI PBX. This board is Blackfin BF537 based. The schematics are not fully opened. Signed-off-by: Dimitar Penev Signed-off-by: Mike Frysinger --- v2 - rebased and applied feedback from Wolfgang MAINTAINERS | 4 + board/pr1/Makefile | 50 ++++++++++++++++ board/pr1/config.mk | 30 +++++++++ board/pr1/pr1.c | 30 +++++++++ boards.cfg | 1 + include/configs/pr1.h | 157 +++++++++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 272 insertions(+), 0 deletions(-) create mode 100644 board/pr1/Makefile create mode 100644 board/pr1/config.mk create mode 100644 board/pr1/pr1.c create mode 100644 include/configs/pr1.h diff --git a/MAINTAINERS b/MAINTAINERS index 4bf12b5..3f83189 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1154,6 +1154,10 @@ Chong Huang bf525-ucr2 BF525 +Dimitar Penev + + PR1 Appliance BF537 + ######################################################################### # NDS32 Systems: # # # diff --git a/board/pr1/Makefile b/board/pr1/Makefile new file mode 100644 index 0000000..6ae998f --- /dev/null +++ b/board/pr1/Makefile @@ -0,0 +1,50 @@ +# +# U-boot - Makefile +# +# Copyright (c) Switchfin Org. +# +# Copyright (c) 2005-2007 Analog Device Inc. +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y := $(BOARD).o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/pr1/config.mk b/board/pr1/config.mk new file mode 100644 index 0000000..9d66d26 --- /dev/null +++ b/board/pr1/config.mk @@ -0,0 +1,30 @@ +# +# Copyright (c) Switchfin Org. +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +CFLAGS_lib += -O2 +CFLAGS_lib/lzma += -O2 +CFLAGS_lib/zlib += -O2 diff --git a/board/pr1/pr1.c b/board/pr1/pr1.c new file mode 100644 index 0000000..bb907f3 --- /dev/null +++ b/board/pr1/pr1.c @@ -0,0 +1,30 @@ +/* + * U-boot - main board file + * + * Copyright (c) Switchfin Org. + * + * Copyright (c) 2005-2008 Analog Devices Inc. + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Licensed under the GPL-2 or later. + */ + +#include +#include +#include + +int checkboard(void) +{ + printf("Board: Switchvoice PR1 Appliance\n"); + printf(" Support: http://www.switchvoice.com/\n"); + return 0; +} + +#ifdef CONFIG_BFIN_MAC +int board_eth_init(bd_t *bis) +{ + return bfin_EMAC_initialize(bis); +} +#endif diff --git a/boards.cfg b/boards.cfg index 0b32532..2e819e9 100644 --- a/boards.cfg +++ b/boards.cfg @@ -286,6 +286,7 @@ cm-bf561 blackfin blackfin dnp5370 blackfin blackfin ibf-dsp561 blackfin blackfin ip04 blackfin blackfin +pr1 blackfin blackfin tcm-bf518 blackfin blackfin tcm-bf537 blackfin blackfin M52277EVB m68k mcf5227x m52277evb freescale - M52277EVB:SYS_SPANSION_BOOT,SYS_TEXT_BASE=0x00000000 diff --git a/include/configs/pr1.h b/include/configs/pr1.h new file mode 100644 index 0000000..03d4269 --- /dev/null +++ b/include/configs/pr1.h @@ -0,0 +1,157 @@ +/* + * U-boot - Configuration file for PR1 Appliance + * + * based on bf537-stamp.h + * Copyright (c) Switchfin Org. + */ + +#ifndef __CONFIG_PR1_H__ +#define __CONFIG_PR1_H__ + +#include + + +/* + * Processor Settings + */ +#define CONFIG_BFIN_CPU bf537-0.3 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER + + +/* + * Clock Settings + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV + */ +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 25000000 +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ +/* 1 = CLKIN / 2 */ +#define CONFIG_CLKIN_HALF 0 +/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ +/* 1 = bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ +/* Values can range from 0-63 (where 0 means 64) */ +#define CONFIG_VCO_MULT 24 +/* CCLK_DIV controls the core clock divider */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* SCLK_DIV controls the system clock divider */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 5 + + +/* + * Memory Settings + */ +#define CONFIG_MEM_ADD_WDTH 11 +#define CONFIG_MEM_SIZE 128 + +#define CONFIG_EBIU_SDRRC_VAL 0x306 +#define CONFIG_EBIU_SDGCTL_VAL 0x8091998d + +#define CONFIG_EBIU_AMGCTL_VAL 0xFF +#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 +#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MALLOC_LEN (384 * 1024) + + +/* + * Network Settings + */ +#ifndef __ADSPBF534__ +#define ADI_CMDS_NETWORK 1 +#define CONFIG_BFIN_MAC +#define CONFIG_NETCONSOLE +#endif +#define CONFIG_HOSTNAME pr1 +#define CONFIG_TFTP_BLOCKSIZE 4404 +/* Uncomment next line to use fixed MAC address */ +/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ + + +/* + * Flash Settings + */ +#define CONFIG_SYS_NO_FLASH /* We have no parallel FLASH */ + + +/* + * SPI Settings + */ +#define CONFIG_BFIN_SPI +#define CONFIG_ENV_SPI_MAX_HZ 30000000 +#define CONFIG_SF_DEFAULT_SPEED 30000000 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO + + +/* + * Env Storage Settings + */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET 0x10000 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_IS_EMBEDDED_IN_LDR + + +/* + * I2C Settings + */ +#define CONFIG_BFIN_TWI_I2C +#define CONFIG_HARD_I2C + + +/* + * NAND Settings + */ +#define CONFIG_NAND_PLAT +#define CONFIG_SYS_NAND_BASE 0x20000000 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) +#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1)) +#define BFIN_NAND_WRITE(addr, cmd) \ + do { \ + bfin_write8(addr, cmd); \ + SSYNC(); \ + } while (0) + +#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd) +#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd) +#define NAND_PLAT_GPIO_DEV_READY GPIO_PF9 + +/* + * Misc Settings + */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_RTC_BFIN +#define CONFIG_UART_CONSOLE 0 +#define CONFIG_SYS_PROMPT "pr1>" +#define CONFIG_BOOTCOMMAND "run nandboot" +#define CONFIG_BOOTDELAY 2 +#define CONFIG_LOADADDR 0x2000000 + + +/* + * Pull in common ADI header for remaining command/environment setup + */ +#include + +/* + * Overwrite some settings defined in bfin_adi_common.h + */ +#undef NAND_ENV_SETTINGS +#define NAND_ENV_SETTINGS \ + "nandargs=set bootargs " CONFIG_BOOTARGS "\0" \ + "nandboot=" \ + "nand read $(loadaddr) 0x0 0x900000;" \ + "run nandargs;" \ + "bootm" \ + "\0" + +#endif