From patchwork Mon Dec 5 22:12:30 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabe Black X-Patchwork-Id: 129448 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 0497F1007D4 for ; Tue, 6 Dec 2011 09:12:42 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A728F28150; Mon, 5 Dec 2011 23:12:40 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 1aL8w3xDweYL; Mon, 5 Dec 2011 23:12:40 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id ADE8D2811B; Mon, 5 Dec 2011 23:12:39 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 19ED92811B for ; Mon, 5 Dec 2011 23:12:39 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Z40W6Eeje+WI for ; Mon, 5 Dec 2011 23:12:37 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-gx0-f202.google.com (mail-gx0-f202.google.com [209.85.161.202]) by theia.denx.de (Postfix) with ESMTPS id 229DE280F1 for ; Mon, 5 Dec 2011 23:12:35 +0100 (CET) Received: by ggnp2 with SMTP id p2so763513ggn.3 for ; Mon, 05 Dec 2011 14:12:34 -0800 (PST) Received: by 10.101.148.29 with SMTP id a29mr7062422ano.22.1323123154635; Mon, 05 Dec 2011 14:12:34 -0800 (PST) Received: by 10.101.148.29 with SMTP id a29mr7062395ano.22.1323123154287; Mon, 05 Dec 2011 14:12:34 -0800 (PST) Received: from wpzn3.hot.corp.google.com (216-239-44-65.google.com [216.239.44.65]) by gmr-mx.google.com with ESMTPS id u11si6416080anh.3.2011.12.05.14.12.34 (version=TLSv1/SSLv3 cipher=AES128-SHA); Mon, 05 Dec 2011 14:12:34 -0800 (PST) Received: from wpaz5.hot.corp.google.com (wpaz5.hot.corp.google.com [172.24.198.69]) by wpzn3.hot.corp.google.com (Postfix) with ESMTPS id 3514F10004D; Mon, 5 Dec 2011 14:12:34 -0800 (PST) Received: from gabeblack.mtv.corp.google.com (gabeblack.mtv.corp.google.com [172.22.72.31]) by wpaz5.hot.corp.google.com with ESMTP id pB5MCW7N005340; Mon, 5 Dec 2011 14:12:33 -0800 Received: by gabeblack.mtv.corp.google.com (Postfix, from userid 134246) id AF3D6200F61; Mon, 5 Dec 2011 14:12:32 -0800 (PST) From: Gabe Black To: U-Boot Mailing List Date: Mon, 5 Dec 2011 14:12:30 -0800 Message-Id: <1323123150-18723-1-git-send-email-gabeblack@chromium.org> X-Mailer: git-send-email 1.7.3.1 X-System-Of-Record: true Subject: [U-Boot] [PATCH] x86: Set up the PCI busses when initializing the coreboot "board" X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de U-boot needs a host controller or "hose" to interact with the PCI busses behind them. This change installs a host controller during initialization of the coreboot "board" which implements some of X86's basic PCI semantics. This relies on some existing generic code, but also duplicates a little bit of code from the sc520 implementation. Ideally we'd eliminate that duplication at some point. It looks like in order to scan buses beyond bus 0, we'll need to tell u-boot's generic PCI configuration code what to do if it encounters a bridge, specifically to scan the bus on the other side of it. A hook is installed to configure PCI bus bridges as they encountered by u-boot. The hook extracts the secondary bus number from the bridge's config space and then recursively scans that bus. Signed-off-by: Gabe Black --- board/chromebook-x86/coreboot/coreboot_pci.c | 33 ++++++++++++++++++++++++++ 1 files changed, 33 insertions(+), 0 deletions(-) diff --git a/board/chromebook-x86/coreboot/coreboot_pci.c b/board/chromebook-x86/coreboot/coreboot_pci.c index 732ca3c..2ec6059 100644 --- a/board/chromebook-x86/coreboot/coreboot_pci.c +++ b/board/chromebook-x86/coreboot/coreboot_pci.c @@ -25,6 +25,39 @@ * MA 02111-1307 USA */ +#include +#include +#include + +static struct pci_controller coreboot_hose; + +#define X86_PCI_CONFIG_ADDR 0xCF8 +#define X86_PCI_CONFIG_DATA 0xCFC + +static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev, + struct pci_config_table *table) +{ + u8 secondary; + hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary); + hose->last_busno = max(hose->last_busno, secondary); + pci_hose_scan_bus(hose, secondary); +} + +static struct pci_config_table pci_coreboot_config_table[] = { + /* vendor, device, class, bus, dev, func */ + { PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI, + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, &config_pci_bridge}, + {} +}; + void pci_init_board(void) { + coreboot_hose.config_table = pci_coreboot_config_table; + coreboot_hose.first_busno = 0; + coreboot_hose.last_busno = 0; + coreboot_hose.region_count = 0; + + pci_setup_type1(&coreboot_hose); + pci_register_hose(&coreboot_hose); + pci_hose_scan(&coreboot_hose); }