From patchwork Thu Nov 24 13:57:49 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Schwierzeck X-Patchwork-Id: 127520 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 1DCE51007DD for ; Fri, 25 Nov 2011 00:58:54 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5A4592825F; Thu, 24 Nov 2011 14:58:42 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id jl5TQzZ4BvfB; Thu, 24 Nov 2011 14:58:42 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 70CB628260; Thu, 24 Nov 2011 14:58:23 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 19C9428212 for ; Thu, 24 Nov 2011 14:58:16 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 0PX5hGbQ+CMg for ; Thu, 24 Nov 2011 14:58:15 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-bw0-f44.google.com (mail-bw0-f44.google.com [209.85.214.44]) by theia.denx.de (Postfix) with ESMTPS id 4AD0A281E8 for ; Thu, 24 Nov 2011 14:58:10 +0100 (CET) Received: by mail-bw0-f44.google.com with SMTP id zv15so2608936bkb.3 for ; Thu, 24 Nov 2011 05:58:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=WkoXayDL/tjRPNRqBlhApWUaEdNItj4dU5A2itBcTG8=; b=DFPnfixmCjEph96RQWTJiQpKIMCwjmqvUU8fFdk1dvs5Hb2BzKwkA/YdSLfHz+xoVI c4rSBGUpW0NebXPxhYXXJVeX3ACwxKSJPfHLFnIANY3xmlcqAHkUWIpy/G9TFOScQKnh aHyrk2kqGdLq4ly1mAbRMPSmW6spNZLLhC2rE= Received: by 10.204.15.200 with SMTP id l8mr14214624bka.132.1322143089954; Thu, 24 Nov 2011 05:58:09 -0800 (PST) Received: from pc000853.sas.sys.sphairon.com (dslb-088-073-225-170.pools.arcor-ip.net. [88.73.225.170]) by mx.google.com with ESMTPS id hy13sm15911381bkc.0.2011.11.24.05.58.08 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 24 Nov 2011 05:58:09 -0800 (PST) From: Daniel Schwierzeck To: u-boot@lists.denx.de Date: Thu, 24 Nov 2011 14:57:49 +0100 Message-Id: <1322143076-20349-5-git-send-email-daniel.schwierzeck@googlemail.com> X-Mailer: git-send-email 1.7.7.2 In-Reply-To: <1322143076-20349-1-git-send-email-daniel.schwierzeck@googlemail.com> References: <1322143076-20349-1-git-send-email-daniel.schwierzeck@googlemail.com> Cc: Thomas Langer , Shinya Kuribayashi Subject: [U-Boot] [PATCH 04/11] MIPS: add register definition for EBase register X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de The CPUNum field in the Ebase register contains an unique identifier for each CPU. This helps to distinguish between CPU cores in multi-processor systems. Signed-off-by: Daniel Schwierzeck --- arch/mips/include/asm/mipsregs.h | 13 +++++++++++++ 1 files changed, 13 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index be7e5c6..15a9fd5 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -89,6 +89,13 @@ #define CP0_DWATCH $19 /* + * Additional Coprocessor 0 register names. + * These registers are listed for completeness and are intended + * for usage in assembly code. + */ +#define CP0_EBASE $15,1 + +/* * Coprocessor 0 Set 1 register names */ #define CP0_S1_DERRADDR0 $26 @@ -395,6 +402,12 @@ #define CAUSEF_BD (_ULCAST_(1) << 31) /* + * Bits in the coprocessor 0 EBase register. + */ +#define EBASEB_CPUNUM 0 +#define EBASEF_CPUNUM (_ULCAST_(1023)) + +/* * Bits in the coprocessor 0 config register. */ /* Generic bits. */