@@ -38,7 +38,6 @@
*/
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
-#define CONFIG_OMAP3430 1 /* which is in a 3430 */
#define CONFIG_CM_T3X 1 /* working with CM-T35 and CM-T3730 */
#define CONFIG_SYS_TEXT_BASE 0x80008000
@@ -34,7 +34,6 @@
/* High Level Configuration Options */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
-#define CONFIG_OMAP3430 1 /* which is in a 3430 */
#define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */
#define CONFIG_SYS_TEXT_BASE 0x80008000
@@ -45,7 +45,6 @@
*/
#define CONFIG_OMAP /* in a TI OMAP core */
#define CONFIG_OMAP34XX /* which is a 34XX */
-#define CONFIG_OMAP3430 /* which is in a 3430 */
#define CONFIG_SYS_TEXT_BASE 0x80008000
@@ -27,7 +27,6 @@
*/
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
-#define CONFIG_OMAP3430 1 /* which is in a 3430 */
#define CONFIG_OMAP3_IGEP0020 1 /* working with IGEP0020 */
#define CONFIG_SDRC /* The chip has SDRC controller */
@@ -27,7 +27,6 @@
*/
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
-#define CONFIG_OMAP3430 1 /* which is in a 3430 */
#define CONFIG_OMAP3_IGEP0030 1 /* working with IGEP0030 */
#define CONFIG_SDRC /* The chip has SDRC controller */
@@ -33,7 +33,6 @@
*/
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
-#define CONFIG_OMAP3430 1 /* which is in a 3430 */
#define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */
#define CONFIG_SDRC /* The chip has SDRC controller */
@@ -22,7 +22,6 @@
*/
#define CONFIG_OMAP /* This is TI OMAP core */
#define CONFIG_OMAP34XX /* belonging to 34XX family */
-#define CONFIG_OMAP3430 /* which is in a 3430 */
#define CONFIG_SDRC /* The chip has SDRC controller */
@@ -37,7 +37,6 @@
#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
-#define CONFIG_OMAP3430 1 /* which is in a 3430 */
#define CONFIG_MVBLX 1 /* working with mvBlueLYNX-X */
#define CONFIG_MACH_TYPE MACH_TYPE_MVBLX
@@ -25,7 +25,6 @@
*/
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
-#define CONFIG_OMAP3430 1 /* which is in a 3430 */
#define CONFIG_OMAP3_OVERO 1 /* working with overo */
#define CONFIG_SDRC /* The chip has SDRC controller */
@@ -28,7 +28,6 @@
*/
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
-#define CONFIG_OMAP3430 1 /* which is in a 3430 */
#define CONFIG_OMAP3_PANDORA 1 /* working with pandora */
#define CONFIG_SDRC /* The chip has SDRC controller */
@@ -38,7 +38,6 @@
*/
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
-#define CONFIG_OMAP3430 1 /* which is in a 3430 */
#define CONFIG_OMAP3_3430SDP 1 /* working with SDP Rev2 */
#define CONFIG_SDRC /* The chip has SDRC controller */
@@ -34,7 +34,6 @@
*/
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
-#define CONFIG_OMAP3430 1 /* which is in a 3430 */
#define CONFIG_OMAP3_ZOOM1 1 /* working with Zoom MDK Rev1 */
#define CONFIG_SDRC /* The chip has SDRC controller */
@@ -35,7 +35,6 @@
*/
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
-#define CONFIG_OMAP3430 1 /* which is in a 3430 */
#define CONFIG_OMAP3_ZOOM2 1 /* working with Zoom II */
#define CONFIG_SDRC /* The chip has SDRC controller */