From patchwork Sun Nov 20 18:01:35 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: York Sun X-Patchwork-Id: 126657 X-Patchwork-Delegate: galak@kernel.crashing.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 5D5CFB722D for ; Mon, 21 Nov 2011 05:01:50 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5D661286AC; Sun, 20 Nov 2011 19:01:48 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 7j4btGqUb5YC; Sun, 20 Nov 2011 19:01:48 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0D5722853E; Sun, 20 Nov 2011 19:01:46 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 37FB02853E for ; Sun, 20 Nov 2011 19:01:43 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id xSptbf+ffab9 for ; Sun, 20 Nov 2011 19:01:42 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from TX2EHSOBE005.bigfish.com (tx2ehsobe003.messaging.microsoft.com [65.55.88.13]) by theia.denx.de (Postfix) with ESMTPS id E7E0E2853C for ; Sun, 20 Nov 2011 19:01:40 +0100 (CET) Received: from mail97-tx2-R.bigfish.com (10.9.14.243) by TX2EHSOBE005.bigfish.com (10.9.40.25) with Microsoft SMTP Server id 14.1.225.22; Sun, 20 Nov 2011 18:01:01 +0000 Received: from mail97-tx2 (localhost.localdomain [127.0.0.1]) by mail97-tx2-R.bigfish.com (Postfix) with ESMTP id 707305483ED for ; Sun, 20 Nov 2011 18:01:22 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275bhz2dh2a8h668h839h61h) X-Spam-TCS-SCL: 0:0 X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPVD:NLI; H:mail.freescale.net; RD:none; EFVD:NLI Received: from mail97-tx2 (localhost.localdomain [127.0.0.1]) by mail97-tx2 (MessageSwitch) id 1321812082117562_23073; Sun, 20 Nov 2011 18:01:22 +0000 (UTC) Received: from TX2EHSMHS042.bigfish.com (unknown [10.9.14.253]) by mail97-tx2.bigfish.com (Postfix) with ESMTP id 0D85DBB804C for ; Sun, 20 Nov 2011 18:01:22 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by TX2EHSMHS042.bigfish.com (10.9.99.142) with Microsoft SMTP Server (TLS) id 14.1.225.22; Sun, 20 Nov 2011 18:01:01 +0000 Received: from az33smr01.freescale.net (10.64.34.199) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server id 14.1.339.2; Sun, 20 Nov 2011 12:01:37 -0600 Received: from localhost.localdomain ([10.214.81.149]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id pAKI1aic024436; Sun, 20 Nov 2011 12:01:36 -0600 (CST) From: York Sun To: Date: Sun, 20 Nov 2011 10:01:35 -0800 Message-ID: <1321812095-22119-1-git-send-email-yorksun@freescale.com> X-Mailer: git-send-email 1.7.0.4 MIME-Version: 1.0 X-OriginatorOrg: freescale.com Cc: York Sun Subject: [U-Boot] [PATCH] powerpc/85xx: Add workaround for erratum A-003474 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Erratum A-003474: Internal DDR calibration circuit is not supported Impact: Experience shows no significant benefit to device operation with auto-calibration enabled versus it disabled. To ensure consistent timing results, Freescale recommends this feature be disabled in future customer products. There should be no impact to parts that are already operating in the field. Workaround: Prior to setting DDR_SDRAM_CFG[MEM_EN]=1, do the following: 1. Write a value of 0x0000_0015 to the register at offset CCSRBAR + DDR OFFSET + 0xf30 2. Write a value of 0x2400_0000 to the register at offset CCSRBAR + DDR OFFSET + 0xf54 Signed-off-by: York Sun --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 +++ arch/powerpc/cpu/mpc85xx/ddr-gen3.c | 5 +++++ arch/powerpc/include/asm/config_mpc85xx.h | 7 +++++++ 3 files changed, 15 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index f7c0934..1da5fe4 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -56,6 +56,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999) puts("Work-around for Erratum CPU-A003999 enabled\n"); #endif +#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_A003474) + puts("Work-around for Erratum DDR-A003473 enabled\n"); +#endif #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN) puts("Work-around for DDR MSYNC_IN Erratum enabled\n"); #endif diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c index c8c84a1..18e9cc5 100644 --- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c +++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c @@ -115,6 +115,11 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, for (i = 0; i < 32; i++) out_be32(&ddr->debug[i], regs->debug[i]); +#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474 + out_be32(&ddr->debug[12], 0x00000015); + out_be32(&ddr->debug[21], 0x24000000); +#endif /* CONFIG_SYS_FSL_ERRATUM_DDR_A003474 */ + /* Set, but do not enable the memory */ temp_sdram_cfg = regs->ddr_sdram_cfg; temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN); diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index dba9eda..2d73458 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -317,6 +317,7 @@ #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_USB138 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 +#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 #elif defined(CONFIG_PPC_P2041) #define CONFIG_MAX_CPUS 4 @@ -337,6 +338,7 @@ #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_USB138 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 +#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 #elif defined(CONFIG_PPC_P3041) #define CONFIG_MAX_CPUS 4 @@ -357,6 +359,7 @@ #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_USB138 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 +#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 #elif defined(CONFIG_PPC_P3060) #define CONFIG_MAX_CPUS 8 @@ -384,6 +387,7 @@ #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 +#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 #elif defined(CONFIG_PPC_P4080) #define CONFIG_MAX_CPUS 8 @@ -413,6 +417,7 @@ #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 +#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 /* P5010 is single core version of P5020 */ #elif defined(CONFIG_PPC_P5010) @@ -433,6 +438,7 @@ #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_USB138 +#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 #elif defined(CONFIG_PPC_P5020) #define CONFIG_MAX_CPUS 2 @@ -452,6 +458,7 @@ #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_USB138 +#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 #else #error Processor type not defined for this platform