From patchwork Tue Nov 8 18:12:17 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Rini X-Patchwork-Id: 124411 X-Patchwork-Delegate: s-paulraj@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id E371DB6F98 for ; Wed, 9 Nov 2011 05:14:11 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 978B829A51; Tue, 8 Nov 2011 19:13:34 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ix4MxipkcsaY; Tue, 8 Nov 2011 19:13:34 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0327F29B30; Tue, 8 Nov 2011 19:13:08 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0CAFC28CC3 for ; Tue, 8 Nov 2011 19:13:03 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id gK1a+9Y2umL3 for ; Tue, 8 Nov 2011 19:13:00 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from arroyo.ext.ti.com (arroyo.ext.ti.com [192.94.94.40]) by theia.denx.de (Postfix) with ESMTPS id 1374E29A7B for ; Tue, 8 Nov 2011 19:12:34 +0100 (CET) Received: from dbdp20.itg.ti.com ([172.24.170.38]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id pA8ICUb5010624 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Tue, 8 Nov 2011 12:12:32 -0600 Received: from DBDE70.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id pA8ICUD1013011 for ; Tue, 8 Nov 2011 23:42:30 +0530 (IST) Received: from dbdp31.itg.ti.com (172.24.170.98) by dbde70.ent.ti.com (172.24.170.148) with Microsoft SMTP Server id 14.1.323.3; Tue, 8 Nov 2011 23:42:29 +0530 Received: from localhost.localdomain (dbdp20.itg.ti.com [172.24.170.38]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id pA8ICDJ0022665 for ; Tue, 8 Nov 2011 23:42:28 +0530 (IST) From: Tom Rini To: Date: Tue, 8 Nov 2011 11:12:17 -0700 Message-ID: <1320775941-28773-9-git-send-email-trini@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1320775941-28773-1-git-send-email-trini@ti.com> References: <1320775941-28773-1-git-send-email-trini@ti.com> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v2 08/12] OMAP3 SPL: Add identify_pop_memory function X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de A number of boards are populated with a PoP chip for both DDR and NAND memory. So to determine DDR timings the NAND chip needs to be probed and mfr/id returned to the board to make decisions with. All of this code is put into spl_pop_probe.c and controlled via CONFIG_SPL_OMAP3_POP_PROBE. Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/omap3/Makefile | 3 + arch/arm/cpu/armv7/omap3/spl_pop_probe.c | 83 +++++++++++++++++++++++++++ arch/arm/include/asm/arch-omap3/sys_proto.h | 1 + 3 files changed, 87 insertions(+), 0 deletions(-) create mode 100644 arch/arm/cpu/armv7/omap3/spl_pop_probe.c diff --git a/arch/arm/cpu/armv7/omap3/Makefile b/arch/arm/cpu/armv7/omap3/Makefile index 8e85891..772f3d4 100644 --- a/arch/arm/cpu/armv7/omap3/Makefile +++ b/arch/arm/cpu/armv7/omap3/Makefile @@ -31,6 +31,9 @@ COBJS += board.o COBJS += clock.o COBJS += mem.o COBJS += sys_info.o +ifdef CONFIG_SPL_BUILD +COBJS-$(CONFIG_SPL_OMAP3_POP_PROBE) += spl_pop_probe.o +endif COBJS-$(CONFIG_EMIF4) += emif4.o COBJS-$(CONFIG_SDRC) += sdrc.o diff --git a/arch/arm/cpu/armv7/omap3/spl_pop_probe.c b/arch/arm/cpu/armv7/omap3/spl_pop_probe.c new file mode 100644 index 0000000..0c79df5 --- /dev/null +++ b/arch/arm/cpu/armv7/omap3/spl_pop_probe.c @@ -0,0 +1,83 @@ +/* + * (C) Copyright 2011 + * Texas Instruments, + * + * Author : + * Tom Rini + * + * Initial Code from: + * Richard Woodruff + * Jian Zhang + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +static struct gpmc *gpmc_config = (struct gpmc *)GPMC_BASE; + +/* nand_command: Send a flash command to the flash chip */ +static void nand_command(u8 command) +{ + writeb(command, &gpmc_config->cs[0].nand_cmd); + + if (command == NAND_CMD_RESET) { + unsigned char ret_val; + writeb(NAND_CMD_STATUS, &gpmc_config->cs[0].nand_cmd); + do { + /* Wait until ready */ + ret_val = readl(&gpmc_config->cs[0].nand_dat); + } while ((ret_val & NAND_STATUS_READY) != NAND_STATUS_READY); + } +} + +/* + * Many boards ship with a PoP chip of both NAND and DDR, so we need + * probe the NAND side, very early, to see what it says and pass this + * along to the board. The board code will then use this information + * to decide what DDR timings to use. + */ +void identify_pop_memory(int *mfr, int *id) +{ + /* Make sure that we have setup GPMC for NAND correctly. */ + writel(M_NAND_GPMC_CONFIG1, &gpmc_config->cs[0].config1); + writel(M_NAND_GPMC_CONFIG2, &gpmc_config->cs[0].config2); + writel(M_NAND_GPMC_CONFIG3, &gpmc_config->cs[0].config3); + writel(M_NAND_GPMC_CONFIG4, &gpmc_config->cs[0].config4); + writel(M_NAND_GPMC_CONFIG5, &gpmc_config->cs[0].config5); + writel(M_NAND_GPMC_CONFIG6, &gpmc_config->cs[0].config6); + + /* Enable the GPMC Mapping */ + writel((((GPMC_SIZE_128M & 0xF) << 8) | ((NAND_BASE >> 24) & 0x3F) | + (1 << 6)), &gpmc_config->cs[0].config7); + + sdelay(2000); + + /* Issue a RESET and then READID */ + nand_command(NAND_CMD_RESET); + nand_command(NAND_CMD_READID); + + /* Set the address to read to 0x0 */ + writeb(0x0, &gpmc_config->cs[0].nand_adr); + + /* Read off the manufacturer and device id. */ + *mfr = readb(&gpmc_config->cs[0].nand_dat); + *id = readb(&gpmc_config->cs[0].nand_dat); +} diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index 80e167b..efa13df 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -40,6 +40,7 @@ void sdrc_init(void); void do_sdrc_init(u32, u32); void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, u32 *mr); +void identify_pop_memory(int *mfr, int *id); void emif4_init(void); void gpmc_init(void); void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,