From patchwork Tue Nov 8 18:12:19 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Rini X-Patchwork-Id: 124414 X-Patchwork-Delegate: s-paulraj@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id DE21BB6F83 for ; Wed, 9 Nov 2011 05:14:46 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id AE79F28E66; Tue, 8 Nov 2011 19:13:51 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id C2tznzEmXO4I; Tue, 8 Nov 2011 19:13:51 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3BF6529BDF; Tue, 8 Nov 2011 19:13:13 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9779B299F6 for ; Tue, 8 Nov 2011 19:13:07 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id i0B6LZG9ItYp for ; Tue, 8 Nov 2011 19:13:07 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from comal.ext.ti.com (comal.ext.ti.com [198.47.26.152]) by theia.denx.de (Postfix) with ESMTPS id 0895B29B30 for ; Tue, 8 Nov 2011 19:12:38 +0100 (CET) Received: from dbdp20.itg.ti.com ([172.24.170.38]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id pA8ICYW1029376 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Tue, 8 Nov 2011 12:12:36 -0600 Received: from DBDE71.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id pA8ICYTH013026 for ; Tue, 8 Nov 2011 23:42:34 +0530 (IST) Received: from dbdp31.itg.ti.com (172.24.170.98) by DBDE71.ent.ti.com (172.24.170.149) with Microsoft SMTP Server id 14.1.323.3; Tue, 8 Nov 2011 23:42:34 +0530 Received: from localhost.localdomain (dbdp20.itg.ti.com [172.24.170.38]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id pA8ICDJ2022665 for ; Tue, 8 Nov 2011 23:42:32 +0530 (IST) From: Tom Rini To: Date: Tue, 8 Nov 2011 11:12:19 -0700 Message-ID: <1320775941-28773-11-git-send-email-trini@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1320775941-28773-1-git-send-email-trini@ti.com> References: <1320775941-28773-1-git-send-email-trini@ti.com> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v2 10/12] OMAP3: Add SPL support to omap3_evm X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Add Hynix 200MHz timing information to . We don't calculate the MCFG value here for the Micron parts as the provided one assumes a memory size which is incorrect. This also changes CONFIG_SYS_TEXT_BASE to 0x80100000. Signed-off-by: Tom Rini --- arch/arm/include/asm/arch-omap3/mem.h | 23 +++++++++++++++++ board/ti/evm/config.mk | 33 ------------------------- board/ti/evm/evm.c | 42 ++++++++++++++++++++++++++++++- include/configs/omap3_evm.h | 27 ++++++++++++++++++++ include/configs/omap3_evm_common.h | 28 +++++++++++++++++++++ include/configs/omap3_evm_quick_mmc.h | 10 +++++++ include/configs/omap3_evm_quick_nand.h | 22 ++++++++++++++++ 7 files changed, 150 insertions(+), 35 deletions(-) delete mode 100644 board/ti/evm/config.mk diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index 2ac15ce..025a1f7 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -92,6 +92,29 @@ enum { ACTIM_CTRLB_TXP(b) | \ ACTIM_CTRLB_TXSR(d) +/* Hynix part of AM/DM37xEVM (200MHz optimized) */ +#define HYNIX_TDAL_200 6 +#define HYNIX_TDPL_200 3 +#define HYNIX_TRRD_200 2 +#define HYNIX_TRCD_200 4 +#define HYNIX_TRP_200 3 +#define HYNIX_TRAS_200 8 +#define HYNIX_TRC_200 11 +#define HYNIX_TRFC_200 18 +#define HYNIX_V_ACTIMA_200 \ + ACTIM_CTRLA(HYNIX_TRFC_200, HYNIX_TRC_200, \ + HYNIX_TRAS_200, HYNIX_TRP_200, \ + HYNIX_TRCD_200, HYNIX_TRRD_200, \ + HYNIX_TDPL_200, HYNIX_TDAL_200) + +#define HYNIX_TWTR_200 2 +#define HYNIX_TCKE_200 1 +#define HYNIX_TXP_200 1 +#define HYNIX_XSR_200 28 +#define HYNIX_V_ACTIMB_200 \ + ACTIM_CTRLB(HYNIX_TWTR_200, HYNIX_TCKE_200, \ + HYNIX_TXP_200, HYNIX_XSR_200) + /* Infineon part of 3430SDP (165MHz optimized) 6.06ns */ #define INFINEON_TDAL_165 6 /* Twr/Tck + Trp/tck */ /* 15/6 + 18/6 = 5.5 -> 6 */ diff --git a/board/ti/evm/config.mk b/board/ti/evm/config.mk deleted file mode 100644 index d173eef..0000000 --- a/board/ti/evm/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2006 - 2008 -# Texas Instruments, -# -# EVM uses OMAP3 (ARM-CortexA8) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -# Physical Address: -# 8000'0000 (bank0) -# A000/0000 (bank1) -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) - -# For use with external or internal boots. -CONFIG_SYS_TEXT_BASE = 0x80008000 diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c index 8c43463..4cf9452 100644 --- a/board/ti/evm/evm.c +++ b/board/ti/evm/evm.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2004-2008 + * (C) Copyright 2004-2011 * Texas Instruments, * * Author : @@ -37,6 +37,7 @@ #include #include #include +#include #include "evm.h" #define OMAP3EVM_GPIO_ETH_RST_GEN1 64 @@ -119,6 +120,43 @@ int board_init(void) return 0; } +#ifdef CONFIG_SPL_BUILD +/* + * Routine: get_board_mem_timings + * Description: If we use SPL then there is no x-loader nor config header + * so we have to setup the DDR timings ourself on the first bank. This + * provides the timing values back to the function that configures + * the memory. + */ +void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, + u32 *mr) +{ + int pop_mfr, pop_id; + + /* + * We need to identify what PoP memory is on the board so that + * we know what timings to use. + */ + identify_pop_memory(&pop_mfr, &pop_id); + + if (pop_mfr == NAND_MFR_HYNIX && pop_id == 0xbc) { + *ctrla = HYNIX_V_ACTIMA_200; + *ctrlb = HYNIX_V_ACTIMB_200; + *mcfg = 0x03588099; + } else { + *ctrla = MICRON_V_ACTIMA_165; + *ctrlb = MICRON_V_ACTIMB_165; + /* + * MICRON_V_MCFG_165 would be correct here except that + * we have 128MB not PHYS_SDRAM_1_SIZE (32MB) + */ + *mcfg = 0x02584099; + } + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + *mr = MICRON_V_MR_165; +} +#endif + /* * Routine: misc_init_r * Description: Init ethernet (done here so udelay works) @@ -238,7 +276,7 @@ int board_eth_init(bd_t *bis) } #endif /* CONFIG_CMD_NET */ -#ifdef CONFIG_GENERIC_MMC +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { omap_mmc_init(0); diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 47ec39f..dc611ca 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -84,6 +84,13 @@ #define CONFIG_GENERIC_MMC #define CONFIG_OMAP_HSMMC #define CONFIG_DOS_PARTITION +/* SPL */ +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" /* USB * @@ -94,6 +101,26 @@ #define CONFIG_MUSB_HCD /* #define CONFIG_MUSB_UDC */ +/* NAND SPL */ +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ + 10, 11, 12, 13} +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ + CONFIG_SYS_NAND_ECCSIZE) +#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ + CONFIG_SYS_NAND_ECCSTEPS) +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + /* ----------------------------------------------------------------------------- * Include common board configuration * ----------------------------------------------------------------------------- diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h index 54aa7a7..5331ae4 100644 --- a/include/configs/omap3_evm_common.h +++ b/include/configs/omap3_evm_common.h @@ -289,4 +289,32 @@ /* Uncomment to define the board revision statically */ /* #define CONFIG_STATIC_BOARD_REV OMAP3EVM_BOARD_GEN_2 */ +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_TEXT_BASE 0x40200800 +#define CONFIG_SPL_MAX_SIZE (45 * 1024) /* 45 KB */ +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK + +#define CONFIG_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_OMAP3_POP_PROBE +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +/* + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x80100000 should not be used for any + * other needs. + */ +#define CONFIG_SYS_TEXT_BASE 0x80100000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 + #endif /* __OMAP3_EVM_COMMON_H */ diff --git a/include/configs/omap3_evm_quick_mmc.h b/include/configs/omap3_evm_quick_mmc.h index 691e4c2..912da7d 100644 --- a/include/configs/omap3_evm_quick_mmc.h +++ b/include/configs/omap3_evm_quick_mmc.h @@ -88,4 +88,14 @@ "root=/dev/mmcblk0p2 rw " \ "rootfstype=ext3 rootwait" +/* + * SPL + */ +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" + #endif /* __OMAP3_EVM_QUICK_MMC_H */ diff --git a/include/configs/omap3_evm_quick_nand.h b/include/configs/omap3_evm_quick_nand.h index 2d18314..2f879c0 100644 --- a/include/configs/omap3_evm_quick_nand.h +++ b/include/configs/omap3_evm_quick_nand.h @@ -76,4 +76,26 @@ "root=/dev/mtdblock4 rw " \ "rootfstype=jffs2 " +/* + * SPL + */ +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ + 10, 11, 12, 13} +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ + CONFIG_SYS_NAND_ECCSIZE) +#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ + CONFIG_SYS_NAND_ECCSTEPS) +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + #endif /* __OMAP3_EVM_QUICK_NAND_H */