From patchwork Mon Oct 24 09:46:32 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Macpaul Lin X-Patchwork-Id: 121313 X-Patchwork-Delegate: macpaul@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id D9151B6F68 for ; Mon, 24 Oct 2011 20:47:05 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3D476280AF; Mon, 24 Oct 2011 11:47:03 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id V2QRwyas0t1h; Mon, 24 Oct 2011 11:47:03 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 37EEF280BE; Mon, 24 Oct 2011 11:47:00 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 69CED286F5 for ; Mon, 24 Oct 2011 11:46:57 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 4VB5ORAgdpwt for ; Mon, 24 Oct 2011 11:46:56 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from atces.andestech.com (59-124-160-118.HINET-IP.hinet.net [59.124.160.118]) by theia.denx.de (Postfix) with ESMTP id B3F9B280AE for ; Mon, 24 Oct 2011 11:46:53 +0200 (CEST) Received: from ATCPCS06.andestech.com (atcpcs06.andestech.com [10.0.1.236]) by atces.andestech.com (Postfix) with ESMTP id D59ED2E20083; Mon, 24 Oct 2011 17:46:50 +0800 (CST) Received: from app01.andestech.com ([10.0.4.31]) by ATCPCS06.andestech.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 24 Oct 2011 17:46:50 +0800 From: Macpaul Lin To: u-boot@lists.denx.de, wd@denx.de, vapier@gentoo.org, macpaul@gmail.com, sjg@chromium.org, robotboy@chromium.org Date: Mon, 24 Oct 2011 17:46:32 +0800 Message-Id: <1319449593-2427-2-git-send-email-macpaul@andestech.com> X-Mailer: git-send-email 1.7.3.5 In-Reply-To: <1319449593-2427-1-git-send-email-macpaul@andestech.com> References: <1319449593-2427-1-git-send-email-macpaul@andestech.com> X-OriginalArrivalTime: 24 Oct 2011 09:46:50.0506 (UTC) FILETIME=[DA9396A0:01CC9231] Cc: Macpaul Lin Subject: [U-Boot] [PATCH 2/3] nds32: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Add ARCH_DMA_MINALIGN definition to asm/cache.h Signed-off-by: Macpaul Lin Acked-by: Anton Staaf --- arch/nds32/include/asm/cache.h | 11 +++++++++++ 1 files changed, 11 insertions(+), 0 deletions(-) diff --git a/arch/nds32/include/asm/cache.h b/arch/nds32/include/asm/cache.h index d769196..fc22c7b 100644 --- a/arch/nds32/include/asm/cache.h +++ b/arch/nds32/include/asm/cache.h @@ -51,4 +51,15 @@ DEFINE_GET_SYS_REG(DCM_CFG); #define DCM_CFG_OFF_DSZ 6 /* D-cache line size */ #define DCM_CFG_MSK_DSZ (0x7UL << DCM_CFG_OFF_DSZ) +/* + * The current upper bound for NDS32 L1 data cache line sizes is 32 bytes. + * We use that value for aligning DMA buffers unless the board config has + * specified an alternate cache line size. + */ +#ifdef CONFIG_SYS_CACHELINE_SIZE +#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE +#else +#define ARCH_DMA_MINALIGN 32 +#endif + #endif /* _ASM_CACHE_H */