From patchwork Wed Oct 12 21:01:46 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anton staaf X-Patchwork-Id: 119299 X-Patchwork-Delegate: info@emk-elektronik.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 8B527B6F7D for ; Thu, 13 Oct 2011 08:04:00 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BB42728A98; Wed, 12 Oct 2011 23:03:34 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id aa4MMCE3hbGu; Wed, 12 Oct 2011 23:03:34 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5B4DE28A6A; Wed, 12 Oct 2011 23:02:39 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D7F2A28455 for ; Wed, 12 Oct 2011 23:02:17 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id edKhnz5JhBdj for ; Wed, 12 Oct 2011 23:02:12 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from smtp-out.google.com (smtp-out.google.com [74.125.121.67]) by theia.denx.de (Postfix) with ESMTPS id BD8D428442 for ; Wed, 12 Oct 2011 23:02:08 +0200 (CEST) Received: from wpaz29.hot.corp.google.com (wpaz29.hot.corp.google.com [172.24.198.93]) by smtp-out.google.com with ESMTP id p9CL22xi029703; Wed, 12 Oct 2011 14:02:03 -0700 Received: from servo.mtv.corp.google.com (servo.mtv.corp.google.com [172.22.72.56]) by wpaz29.hot.corp.google.com with ESMTP id p9CL1wam022633; Wed, 12 Oct 2011 14:02:01 -0700 Received: by servo.mtv.corp.google.com (Postfix, from userid 99248) id 227024A187; Wed, 12 Oct 2011 14:02:01 -0700 (PDT) From: Anton Staaf To: u-boot@lists.denx.de Date: Wed, 12 Oct 2011 14:01:46 -0700 Message-Id: <1318453311-31349-8-git-send-email-robotboy@chromium.org> X-Mailer: git-send-email 1.7.3.1 In-Reply-To: <1318453311-31349-1-git-send-email-robotboy@chromium.org> References: <1318453311-31349-1-git-send-email-robotboy@chromium.org> X-System-Of-Record: true Cc: Anton Staaf Subject: [U-Boot] [PATCH 07/12] avr32: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Signed-off-by: Anton Staaf Cc: Mike Frysinger Cc: Lukasz Majewski Cc: Reinhard Meyer Change-Id: I5965f64804c3938823be716f45298f093871fe83 --- arch/avr32/include/asm/cache.h | 40 ++++++++++++++++++++++++++++++++++++++++ 1 files changed, 40 insertions(+), 0 deletions(-) create mode 100644 arch/avr32/include/asm/cache.h diff --git a/arch/avr32/include/asm/cache.h b/arch/avr32/include/asm/cache.h new file mode 100644 index 0000000..3b2b032 --- /dev/null +++ b/arch/avr32/include/asm/cache.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __AVR32_CACHE_H__ +#define __AVR32_CACHE_H__ + +/* + * Since the AVR32 architecture has a queryable cacheline size with a maximum + * value of 256 we set the DMA buffer alignemnt requirement to this maximum + * value. The board config can override this if it knows that the cacheline + * size is a smaller value. AVR32 boards use the CONFIG_SYS_DCACHE_LINESZ + * macro to specify cache line size, so if it is set we use it instead. + */ +#ifdef CONFIG_SYS_CACHELINE_SIZE +#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE +#elif defined(CONFIG_SYS_DCACHE_LINESZ) +#define ARCH_DMA_MINALIGN CONFIG_SYS_DCACHE_LINESZ +#else +#define ARCH_DMA_MINALIGN 256 +#endif + +#endif /* __AVR32_CACHE_H__ */