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[U-Boot,3/5] tegra: define CONFIG_SYS_CACHELINE_SIZE for tegra

Message ID 1317686100-4905-4-git-send-email-robotboy@chromium.org
State Accepted
Commit 96d21237ec2b799f60a827ea680594b7ebfdac7f
Headers show

Commit Message

Anton staaf Oct. 3, 2011, 11:54 p.m. UTC 
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Tom Warren <twarren.nvidia@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>

Change-Id: I5c4bcfc0bfe59158ff249fe3be6640eec6d3cc76
---
 include/configs/tegra2-common.h |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

Comments

Mike Frysinger Oct. 4, 2011, 3:15 p.m. UTC | #1 
Acked-by: Mike Frysinger <vapier@gentoo.org>
-mike
diff mbox

Patch

diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h
index 73e0f05..a9c665c 100644
--- a/include/configs/tegra2-common.h
+++ b/include/configs/tegra2-common.h
@@ -33,6 +33,8 @@ 
 #define CONFIG_MACH_TEGRA_GENERIC	/* which is a Tegra generic machine */
 #define CONFIG_SYS_L2CACHE_OFF		/* No L2 cache */
 
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
 #define CONFIG_ENABLE_CORTEXA9		/* enable CPU (A9 complex) */
 
 #include <asm/arch/tegra2.h>		/* get chip and board defs */