diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index a0e5dd7..7632745 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -61,7 +61,6 @@ COBJS-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o
 COBJS-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o
 COBJS-$(CONFIG_DRIVER_NETARMETH) += netarm_eth.o
 COBJS-$(CONFIG_NETCONSOLE) += netconsole.o
-COBJS-$(CONFIG_DRIVER_NS7520_ETHERNET) += ns7520_eth.o
 COBJS-$(CONFIG_NS8382X) += ns8382x.o
 COBJS-$(CONFIG_DRIVER_NS9750_ETHERNET) += ns9750_eth.o
 COBJS-$(CONFIG_PCNET) += pcnet.o
diff --git a/drivers/net/ns7520_eth.c b/drivers/net/ns7520_eth.c
deleted file mode 100644
index de82b04..0000000
--- a/drivers/net/ns7520_eth.c
+++ /dev/null
@@ -1,850 +0,0 @@
-/***********************************************************************
- *
- * Copyright (C) 2005 by Videon Central, Inc.
- *
- * $Id$
- * @Author: Arthur Shipkowski
- * @Descr: Ethernet driver for the NS7520. Uses polled Ethernet, like
- *     the older netarmeth driver.  Note that attempting to filter
- *     broadcast and multicast out in the SAFR register will cause
- *     bad things due to released errata.
- * @References: [1] NS7520 Hardware Reference, December 2003
- *		[2] Intel LXT971 Datasheet #249414 Rev. 02
- *
- ***********************************************************************/
-
-#include <common.h>
-
-#include <net.h>		/* NetSendPacket */
-#include <asm/arch/netarm_registers.h>
-#include <asm/arch/netarm_dma_module.h>
-
-#include "ns7520_eth.h"		/* for Ethernet and PHY */
-
-/**
- * Send an error message to the terminal.
- */
-#define ERROR(x) \
-do { \
-	char *__foo = strrchr(__FILE__, '/'); \
-	\
-	printf("%s: %d: %s(): ", (__foo == NULL ? __FILE__ : (__foo + 1)), \
-			__LINE__, __FUNCTION__); \
-	printf x; printf("\n"); \
-} while (0);
-
-/* some definition to make transistion to linux easier */
-
-#define NS7520_DRIVER_NAME	"eth"
-#define KERN_WARNING		"Warning:"
-#define KERN_ERR		"Error:"
-#define KERN_INFO		"Info:"
-
-#if 1
-# define DEBUG
-#endif
-
-#ifdef	DEBUG
-# define printk			printf
-
-# define DEBUG_INIT		0x0001
-# define DEBUG_MINOR		0x0002
-# define DEBUG_RX		0x0004
-# define DEBUG_TX		0x0008
-# define DEBUG_INT		0x0010
-# define DEBUG_POLL		0x0020
-# define DEBUG_LINK		0x0040
-# define DEBUG_MII		0x0100
-# define DEBUG_MII_LOW		0x0200
-# define DEBUG_MEM		0x0400
-# define DEBUG_ERROR		0x4000
-# define DEBUG_ERROR_CRIT	0x8000
-
-static int nDebugLvl = DEBUG_ERROR_CRIT;
-
-# define DEBUG_ARGS0( FLG, a0 ) if( ( nDebugLvl & (FLG) ) == (FLG) ) \
-		printf("%s: " a0, __FUNCTION__, 0, 0, 0, 0, 0, 0 )
-# define DEBUG_ARGS1( FLG, a0, a1 ) if( ( nDebugLvl & (FLG) ) == (FLG)) \
-		printf("%s: " a0, __FUNCTION__, (int)(a1), 0, 0, 0, 0, 0 )
-# define DEBUG_ARGS2( FLG, a0, a1, a2 ) if( (nDebugLvl & (FLG)) ==(FLG))\
-		printf("%s: " a0, __FUNCTION__, (int)(a1), (int)(a2), 0, 0,0,0 )
-# define DEBUG_ARGS3( FLG, a0, a1, a2, a3 ) if((nDebugLvl &(FLG))==(FLG))\
-		printf("%s: "a0,__FUNCTION__,(int)(a1),(int)(a2),(int)(a3),0,0,0)
-# define DEBUG_FN( FLG ) if( (nDebugLvl & (FLG)) == (FLG) ) \
-		printf("\r%s:line %d\n", (int)__FUNCTION__, __LINE__, 0,0,0,0);
-# define ASSERT( expr, func ) if( !( expr ) ) { \
-		printf( "Assertion failed! %s:line %d %s\n", \
-		(int)__FUNCTION__,__LINE__,(int)(#expr),0,0,0); \
-		func }
-#else				/* DEBUG */
-# define printk(...)
-# define DEBUG_ARGS0( FLG, a0 )
-# define DEBUG_ARGS1( FLG, a0, a1 )
-# define DEBUG_ARGS2( FLG, a0, a1, a2 )
-# define DEBUG_ARGS3( FLG, a0, a1, a2, a3 )
-# define DEBUG_FN( n )
-# define ASSERT(expr, func)
-#endif				/* DEBUG */
-
-#define NS7520_MII_NEG_DELAY		(5*CONFIG_SYS_HZ)	/* in s */
-#define TX_TIMEOUT			(5*CONFIG_SYS_HZ)	/* in s */
-#define RX_STALL_WORKAROUND_CNT 100
-
-static int ns7520_eth_reset(void);
-
-static void ns7520_link_auto_negotiate(void);
-static void ns7520_link_update_egcr(void);
-static void ns7520_link_print_changed(void);
-
-/* the PHY stuff */
-
-static char ns7520_mii_identify_phy(void);
-static unsigned short ns7520_mii_read(unsigned short uiRegister);
-static void ns7520_mii_write(unsigned short uiRegister,
-			     unsigned short uiData);
-static unsigned int ns7520_mii_get_clock_divisor(unsigned int
-						 unMaxMDIOClk);
-static unsigned int ns7520_mii_poll_busy(void);
-
-static unsigned int nPhyMaxMdioClock = PHY_MDIO_MAX_CLK;
-static unsigned int uiLastLinkStatus;
-static PhyType phyDetected = PHY_NONE;
-
-/***********************************************************************
- * @Function: eth_init
- * @Return: -1 on failure otherwise 0
- * @Descr: Initializes the ethernet engine and uses either FS Forth's default
- *	   MAC addr or the one in environment
- ***********************************************************************/
-
-int eth_init(bd_t * pbis)
-{
-	unsigned char aucMACAddr[6];
-	char *pcTmp = getenv("ethaddr");
-	char *pcEnd;
-	int i;
-
-	DEBUG_FN(DEBUG_INIT);
-
-	/* no need to check for hardware */
-
-	if (!ns7520_eth_reset())
-		return -1;
-
-	if (NULL == pcTmp)
-		return -1;
-
-	for (i = 0; i < 6; i++) {
-		aucMACAddr[i] =
-		    pcTmp ? simple_strtoul(pcTmp, &pcEnd, 16) : 0;
-		pcTmp = (*pcTmp) ? pcEnd + 1 : pcEnd;
-	}
-
-	/* configure ethernet address */
-
-	*get_eth_reg_addr(NS7520_ETH_SA1) =
-	    aucMACAddr[5] << 8 | aucMACAddr[4];
-	*get_eth_reg_addr(NS7520_ETH_SA2) =
-	    aucMACAddr[3] << 8 | aucMACAddr[2];
-	*get_eth_reg_addr(NS7520_ETH_SA3) =
-	    aucMACAddr[1] << 8 | aucMACAddr[0];
-
-	/* enable hardware */
-
-	*get_eth_reg_addr(NS7520_ETH_MAC1) = NS7520_ETH_MAC1_RXEN;
-	*get_eth_reg_addr(NS7520_ETH_SUPP) = NS7520_ETH_SUPP_JABBER;
-	*get_eth_reg_addr(NS7520_ETH_MAC1) = NS7520_ETH_MAC1_RXEN;
-
-	/* the linux kernel may give packets < 60 bytes, for example arp */
-	*get_eth_reg_addr(NS7520_ETH_MAC2) = NS7520_ETH_MAC2_CRCEN |
-	    NS7520_ETH_MAC2_PADEN | NS7520_ETH_MAC2_HUGE;
-
-	/* Broadcast/multicast allowed; if you don't set this even unicast chokes */
-	/* Based on NS7520 errata documentation */
-	*get_eth_reg_addr(NS7520_ETH_SAFR) =
-	    NS7520_ETH_SAFR_BROAD | NS7520_ETH_SAFR_PRM;
-
-	/* enable receive and transmit FIFO, use 10/100 Mbps MII */
-	*get_eth_reg_addr(NS7520_ETH_EGCR) |=
-	    NS7520_ETH_EGCR_ETXWM_75 |
-	    NS7520_ETH_EGCR_ERX |
-	    NS7520_ETH_EGCR_ERXREG |
-	    NS7520_ETH_EGCR_ERXBR | NS7520_ETH_EGCR_ETX;
-
-	return 0;
-}
-
-/***********************************************************************
- * @Function: eth_send
- * @Return: -1 on timeout otherwise 1
- * @Descr: sends one frame by DMA
- ***********************************************************************/
-
-int eth_send(volatile void *pPacket, int nLen)
-{
-	int i, length32, retval = 1;
-	char *pa;
-	unsigned int *pa32, lastp = 0, rest;
-	unsigned int status;
-
-	pa = (char *) pPacket;
-	pa32 = (unsigned int *) pPacket;
-	length32 = nLen / 4;
-	rest = nLen % 4;
-
-	/* make sure there's no garbage in the last word */
-	switch (rest) {
-	case 0:
-		lastp = pa32[length32 - 1];
-		length32--;
-		break;
-	case 1:
-		lastp = pa32[length32] & 0x000000ff;
-		break;
-	case 2:
-		lastp = pa32[length32] & 0x0000ffff;
-		break;
-	case 3:
-		lastp = pa32[length32] & 0x00ffffff;
-		break;
-	}
-
-	while (((*get_eth_reg_addr(NS7520_ETH_EGSR)) &
-		NS7520_ETH_EGSR_TXREGE)
-	       == 0) {
-	}
-
-	/* write to the fifo */
-	for (i = 0; i < length32; i++)
-		*get_eth_reg_addr(NS7520_ETH_FIFO) = pa32[i];
-
-	/* the last word is written to an extra register, this
-	   starts the transmission */
-	*get_eth_reg_addr(NS7520_ETH_FIFOL) = lastp;
-
-	/* Wait for it to be done */
-	while ((*get_eth_reg_addr(NS7520_ETH_EGSR) & NS7520_ETH_EGSR_TXBC)
-	       == 0) {
-	}
-	status = (*get_eth_reg_addr(NS7520_ETH_ETSR));
-	*get_eth_reg_addr(NS7520_ETH_EGSR) = NS7520_ETH_EGSR_TXBC;	/* Clear it now */
-
-	if (status & NS7520_ETH_ETSR_TXOK) {
-		retval = 0;	/* We're OK! */
-	} else if (status & NS7520_ETH_ETSR_TXDEF) {
-		printf("Deferred, we'll see.\n");
-		retval = 0;
-	} else if (status & NS7520_ETH_ETSR_TXAL) {
-		printf("Late collision error, %d collisions.\n",
-		       (*get_eth_reg_addr(NS7520_ETH_ETSR)) &
-		       NS7520_ETH_ETSR_TXCOLC);
-	} else if (status & NS7520_ETH_ETSR_TXAEC) {
-		printf("Excessive collisions: %d\n",
-		       (*get_eth_reg_addr(NS7520_ETH_ETSR)) &
-		       NS7520_ETH_ETSR_TXCOLC);
-	} else if (status & NS7520_ETH_ETSR_TXAED) {
-		printf("Excessive deferral on xmit.\n");
-	} else if (status & NS7520_ETH_ETSR_TXAUR) {
-		printf("Packet underrun.\n");
-	} else if (status & NS7520_ETH_ETSR_TXAJ) {
-		printf("Jumbo packet error.\n");
-	} else {
-		printf("Error: Should never get here.\n");
-	}
-
-	return (retval);
-}
-
-/***********************************************************************
- * @Function: eth_rx
- * @Return: size of last frame in bytes or 0 if no frame available
- * @Descr: gives one frame to U-Boot which has been copied by DMA engine already
- *	   to NetRxPackets[ 0 ].
- ***********************************************************************/
-
-int eth_rx(void)
-{
-	int i;
-	unsigned short rxlen;
-	unsigned short totrxlen = 0;
-	unsigned int *addr;
-	unsigned int rxstatus, lastrxlen;
-	char *pa;
-
-	/* If RXBR is 1, data block was received */
-	while (((*get_eth_reg_addr(NS7520_ETH_EGSR)) &
-		NS7520_ETH_EGSR_RXBR) == NS7520_ETH_EGSR_RXBR) {
-
-		/* get status register and the length of received block */
-		rxstatus = *get_eth_reg_addr(NS7520_ETH_ERSR);
-		rxlen = (rxstatus & NS7520_ETH_ERSR_RXSIZE) >> 16;
-
-		/* clear RXBR to make fifo available */
-		*get_eth_reg_addr(NS7520_ETH_EGSR) = NS7520_ETH_EGSR_RXBR;
-
-		if (rxstatus & NS7520_ETH_ERSR_ROVER) {
-			printf("Receive overrun, resetting FIFO.\n");
-			*get_eth_reg_addr(NS7520_ETH_EGCR) &=
-			    ~NS7520_ETH_EGCR_ERX;
-			udelay(20);
-			*get_eth_reg_addr(NS7520_ETH_EGCR) |=
-			    NS7520_ETH_EGCR_ERX;
-		}
-		if (rxlen == 0) {
-			printf("Nothing.\n");
-			return 0;
-		}
-
-		addr = (unsigned int *) NetRxPackets[0];
-		pa = (char *) NetRxPackets[0];
-
-		/* read the fifo */
-		for (i = 0; i < rxlen / 4; i++) {
-			*addr = *get_eth_reg_addr(NS7520_ETH_FIFO);
-			addr++;
-		}
-
-		if ((*get_eth_reg_addr(NS7520_ETH_EGSR)) &
-		    NS7520_ETH_EGSR_RXREGR) {
-			/* RXFDB indicates wether the last word is 1,2,3 or 4 bytes long */
-			lastrxlen =
-			    ((*get_eth_reg_addr(NS7520_ETH_EGSR)) &
-			     NS7520_ETH_EGSR_RXFDB_MA) >> 28;
-			*addr = *get_eth_reg_addr(NS7520_ETH_FIFO);
-			switch (lastrxlen) {
-			case 1:
-				*addr &= 0xff000000;
-				break;
-			case 2:
-				*addr &= 0xffff0000;
-				break;
-			case 3:
-				*addr &= 0xffffff00;
-				break;
-			}
-		}
-
-		/* Pass the packet up to the protocol layers. */
-		NetReceive(NetRxPackets[0], rxlen - 4);
-		totrxlen += rxlen - 4;
-	}
-
-	return totrxlen;
-}
-
-/***********************************************************************
- * @Function: eth_halt
- * @Return: n/a
- * @Descr: stops the ethernet engine
- ***********************************************************************/
-
-void eth_halt(void)
-{
-	DEBUG_FN(DEBUG_INIT);
-
-	*get_eth_reg_addr(NS7520_ETH_MAC1) &= ~NS7520_ETH_MAC1_RXEN;
-	*get_eth_reg_addr(NS7520_ETH_EGCR) &= ~(NS7520_ETH_EGCR_ERX |
-						NS7520_ETH_EGCR_ERXDMA |
-						NS7520_ETH_EGCR_ERXREG |
-						NS7520_ETH_EGCR_ERXBR |
-						NS7520_ETH_EGCR_ETX |
-						NS7520_ETH_EGCR_ETXDMA);
-}
-
-/***********************************************************************
- * @Function: ns7520_eth_reset
- * @Return: 0 on failure otherwise 1
- * @Descr: resets the ethernet interface and the PHY,
- *	   performs auto negotiation or fixed modes
- ***********************************************************************/
-
-static int ns7520_eth_reset(void)
-{
-	DEBUG_FN(DEBUG_MINOR);
-
-	/* Reset important registers */
-	*get_eth_reg_addr(NS7520_ETH_EGCR) = 0;	/* Null it out! */
-	*get_eth_reg_addr(NS7520_ETH_MAC1) &= NS7520_ETH_MAC1_SRST;
-	*get_eth_reg_addr(NS7520_ETH_MAC2) = 0;
-	/* Reset MAC */
-	*get_eth_reg_addr(NS7520_ETH_EGCR) |= NS7520_ETH_EGCR_MAC_RES;
-	udelay(5);
-	*get_eth_reg_addr(NS7520_ETH_EGCR) &= ~NS7520_ETH_EGCR_MAC_RES;
-
-	/* reset and initialize PHY */
-
-	*get_eth_reg_addr(NS7520_ETH_MAC1) &= ~NS7520_ETH_MAC1_SRST;
-
-	/* we don't support hot plugging of PHY, therefore we don't reset
-	   phyDetected and nPhyMaxMdioClock here. The risk is if the setting is
-	   incorrect the first open
-	   may detect the PHY correctly but succeding will fail
-	   For reseting the PHY and identifying we have to use the standard
-	   MDIO CLOCK value 2.5 MHz only after hardware reset
-	   After having identified the PHY we will do faster */
-
-	*get_eth_reg_addr(NS7520_ETH_MCFG) =
-	    ns7520_mii_get_clock_divisor(nPhyMaxMdioClock);
-
-	/* reset PHY */
-	ns7520_mii_write(MII_BMCR, BMCR_RESET);
-	ns7520_mii_write(MII_BMCR, 0);
-
-	udelay(3000);		/* [2] p.70 says at least 300us reset recovery time. */
-
-	/* MII clock has been setup to default, ns7520_mii_identify_phy should
-	   work for all */
-
-	if (!ns7520_mii_identify_phy()) {
-		printk(KERN_ERR NS7520_DRIVER_NAME
-		       ": Unsupported PHY, aborting\n");
-		return 0;
-	}
-
-	/* now take the highest MDIO clock possible after detection */
-	*get_eth_reg_addr(NS7520_ETH_MCFG) =
-	    ns7520_mii_get_clock_divisor(nPhyMaxMdioClock);
-
-	/* PHY has been detected, so there can be no abort reason and we can
-	   finish initializing ethernet */
-
-	uiLastLinkStatus = 0xff;	/* undefined */
-
-	ns7520_link_auto_negotiate();
-
-	if (phyDetected == PHY_LXT971A)
-		/* set LED2 to link mode */
-		ns7520_mii_write(PHY_LXT971_LED_CFG,
-				 (PHY_LXT971_LED_CFG_LINK_ACT <<
-				  PHY_LXT971_LED_CFG_SHIFT_LED2) |
-				 (PHY_LXT971_LED_CFG_TRANSMIT <<
-				  PHY_LXT971_LED_CFG_SHIFT_LED1));
-
-	return 1;
-}
-
-/***********************************************************************
- * @Function: ns7520_link_auto_negotiate
- * @Return: void
- * @Descr: performs auto-negotation of link.
- ***********************************************************************/
-
-static void ns7520_link_auto_negotiate(void)
-{
-	unsigned long ulStartJiffies;
-	unsigned short uiStatus;
-
-	DEBUG_FN(DEBUG_LINK);
-
-	/* run auto-negotation */
-	/* define what we are capable of */
-	ns7520_mii_write(MII_ADVERTISE,
-			 LPA_100FULL |
-			 LPA_100HALF |
-			 LPA_10FULL |
-			 LPA_10HALF |
-			 PHY_ANLPAR_PSB_802_3);
-	/* start auto-negotiation */
-	ns7520_mii_write(MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
-
-	/* wait for completion */
-
-	ulStartJiffies = get_timer(0);
-	while (get_timer(0) < ulStartJiffies + NS7520_MII_NEG_DELAY) {
-		uiStatus = ns7520_mii_read(MII_BMSR);
-		if ((uiStatus &
-		     (BMSR_ANEGCOMPLETE | BMSR_LSTATUS)) ==
-		    (BMSR_ANEGCOMPLETE | BMSR_LSTATUS)) {
-			/* lucky we are, auto-negotiation succeeded */
-			ns7520_link_print_changed();
-			ns7520_link_update_egcr();
-			return;
-		}
-	}
-
-	DEBUG_ARGS0(DEBUG_LINK, "auto-negotiation timed out\n");
-	/* ignore invalid link settings */
-}
-
-/***********************************************************************
- * @Function: ns7520_link_update_egcr
- * @Return: void
- * @Descr: updates the EGCR and MAC2 link status after mode change or
- *	   auto-negotation
- ***********************************************************************/
-
-static void ns7520_link_update_egcr(void)
-{
-	unsigned int unEGCR;
-	unsigned int unMAC2;
-	unsigned int unIPGT;
-
-	DEBUG_FN(DEBUG_LINK);
-
-	unEGCR = *get_eth_reg_addr(NS7520_ETH_EGCR);
-	unMAC2 = *get_eth_reg_addr(NS7520_ETH_MAC2);
-	unIPGT =
-	    *get_eth_reg_addr(NS7520_ETH_IPGT) & ~NS7520_ETH_IPGT_IPGT;
-
-	unEGCR &= ~NS7520_ETH_EGCR_EFULLD;
-	unMAC2 &= ~NS7520_ETH_MAC2_FULLD;
-	if ((uiLastLinkStatus & PHY_LXT971_STAT2_DUPLEX_MODE)
-	    == PHY_LXT971_STAT2_DUPLEX_MODE) {
-		unEGCR |= NS7520_ETH_EGCR_EFULLD;
-		unMAC2 |= NS7520_ETH_MAC2_FULLD;
-		unIPGT |= 0x15;	/* see [1] p. 167 */
-	} else
-		unIPGT |= 0x12;	/* see [1] p. 167 */
-
-	*get_eth_reg_addr(NS7520_ETH_MAC2) = unMAC2;
-	*get_eth_reg_addr(NS7520_ETH_EGCR) = unEGCR;
-	*get_eth_reg_addr(NS7520_ETH_IPGT) = unIPGT;
-}
-
-/***********************************************************************
- * @Function: ns7520_link_print_changed
- * @Return: void
- * @Descr: checks whether the link status has changed and if so prints
- *	   the new mode
- ***********************************************************************/
-
-static void ns7520_link_print_changed(void)
-{
-	unsigned short uiStatus;
-	unsigned short uiControl;
-
-	DEBUG_FN(DEBUG_LINK);
-
-	uiControl = ns7520_mii_read(MII_BMCR);
-
-	if ((uiControl & BMCR_ANENABLE) == BMCR_ANENABLE) {
-		/* BMSR_LSTATUS is only set on autonegotiation */
-		uiStatus = ns7520_mii_read(MII_BMSR);
-
-		if (!(uiStatus & BMSR_LSTATUS)) {
-			printk(KERN_WARNING NS7520_DRIVER_NAME
-			       ": link down\n");
-			/* @TODO Linux: carrier_off */
-		} else {
-			/* @TODO Linux: carrier_on */
-			if (phyDetected == PHY_LXT971A) {
-				uiStatus =
-				    ns7520_mii_read(PHY_LXT971_STAT2);
-				uiStatus &=
-				    (PHY_LXT971_STAT2_100BTX |
-				     PHY_LXT971_STAT2_DUPLEX_MODE |
-				     PHY_LXT971_STAT2_AUTO_NEG);
-
-				/* mask out all uninteresting parts */
-			}
-			/* other PHYs must store there link information in
-			   uiStatus as PHY_LXT971 */
-		}
-	} else {
-		/* mode has been forced, so uiStatus should be the same as the
-		   last link status, enforce printing */
-		uiStatus = uiLastLinkStatus;
-		uiLastLinkStatus = 0xff;
-	}
-
-	if (uiStatus != uiLastLinkStatus) {
-		/* save current link status */
-		uiLastLinkStatus = uiStatus;
-
-		/* print new link status */
-
-		printk(KERN_INFO NS7520_DRIVER_NAME
-		       ": link mode %i Mbps %s duplex %s\n",
-		       (uiStatus & PHY_LXT971_STAT2_100BTX) ? 100 : 10,
-		       (uiStatus & PHY_LXT971_STAT2_DUPLEX_MODE) ? "full" :
-		       "half",
-		       (uiStatus & PHY_LXT971_STAT2_AUTO_NEG) ? "(auto)" :
-		       "");
-	}
-}
-
-/***********************************************************************
- * the MII low level stuff
- ***********************************************************************/
-
-/***********************************************************************
- * @Function: ns7520_mii_identify_phy
- * @Return: 1 if supported PHY has been detected otherwise 0
- * @Descr: checks for supported PHY and prints the IDs.
- ***********************************************************************/
-
-static char ns7520_mii_identify_phy(void)
-{
-	unsigned short uiID1;
-	unsigned short uiID2;
-	unsigned char *szName;
-	char cRes = 0;
-
-	DEBUG_FN(DEBUG_MII);
-
-	phyDetected = (PhyType) uiID1 = ns7520_mii_read(MII_PHYSID1);
-
-	switch (phyDetected) {
-	case PHY_LXT971A:
-		szName = "LXT971A";
-		uiID2 = ns7520_mii_read(MII_PHYSID2);
-		nPhyMaxMdioClock = PHY_LXT971_MDIO_MAX_CLK;
-		cRes = 1;
-		break;
-	case PHY_NONE:
-	default:
-		/* in case uiID1 == 0 && uiID2 == 0 we may have the wrong
-		   address or reset sets the wrong NS7520_ETH_MCFG_CLKS */
-
-		uiID2 = 0;
-		szName = "unknown";
-		nPhyMaxMdioClock = PHY_MDIO_MAX_CLK;
-		phyDetected = PHY_NONE;
-	}
-
-	printk(KERN_INFO NS7520_DRIVER_NAME
-	       ": PHY (0x%x, 0x%x) = %s detected\n", uiID1, uiID2, szName);
-
-	return cRes;
-}
-
-/***********************************************************************
- * @Function: ns7520_mii_read
- * @Return: the data read from PHY register uiRegister
- * @Descr: the data read may be invalid if timed out. If so, a message
- *	   is printed but the invalid data is returned.
- *	   The fixed device address is being used.
- ***********************************************************************/
-
-static unsigned short ns7520_mii_read(unsigned short uiRegister)
-{
-	DEBUG_FN(DEBUG_MII_LOW);
-
-	/* write MII register to be read */
-	*get_eth_reg_addr(NS7520_ETH_MADR) =
-	    CONFIG_PHY_ADDR << 8 | uiRegister;
-
-	*get_eth_reg_addr(NS7520_ETH_MCMD) = NS7520_ETH_MCMD_READ;
-
-	if (!ns7520_mii_poll_busy())
-		printk(KERN_WARNING NS7520_DRIVER_NAME
-		       ": MII still busy in read\n");
-	/* continue to read */
-
-	*get_eth_reg_addr(NS7520_ETH_MCMD) = 0;
-
-	return (unsigned short) (*get_eth_reg_addr(NS7520_ETH_MRDD));
-}
-
-/***********************************************************************
- * @Function: ns7520_mii_write
- * @Return: nothing
- * @Descr: writes the data to the PHY register. In case of a timeout,
- *	   no special handling is performed but a message printed
- *	   The fixed device address is being used.
- ***********************************************************************/
-
-static void ns7520_mii_write(unsigned short uiRegister,
-			     unsigned short uiData)
-{
-	DEBUG_FN(DEBUG_MII_LOW);
-
-	/* write MII register to be written */
-	*get_eth_reg_addr(NS7520_ETH_MADR) =
-	    CONFIG_PHY_ADDR << 8 | uiRegister;
-
-	*get_eth_reg_addr(NS7520_ETH_MWTD) = uiData;
-
-	if (!ns7520_mii_poll_busy()) {
-		printf(KERN_WARNING NS7520_DRIVER_NAME
-		       ": MII still busy in write\n");
-	}
-}
-
-/***********************************************************************
- * @Function: ns7520_mii_get_clock_divisor
- * @Return: the clock divisor that should be used in NS7520_ETH_MCFG_CLKS
- * @Descr: if no clock divisor can be calculated for the
- *	   current SYSCLK and the maximum MDIO Clock, a warning is printed
- *	   and the greatest divisor is taken
- ***********************************************************************/
-
-static unsigned int ns7520_mii_get_clock_divisor(unsigned int unMaxMDIOClk)
-{
-	struct {
-		unsigned int unSysClkDivisor;
-		unsigned int unClks;	/* field for NS7520_ETH_MCFG_CLKS */
-	} PHYClockDivisors[] = {
-		{
-		4, NS7520_ETH_MCFG_CLKS_4}, {
-		6, NS7520_ETH_MCFG_CLKS_6}, {
-		8, NS7520_ETH_MCFG_CLKS_8}, {
-		10, NS7520_ETH_MCFG_CLKS_10}, {
-		14, NS7520_ETH_MCFG_CLKS_14}, {
-		20, NS7520_ETH_MCFG_CLKS_20}, {
-		28, NS7520_ETH_MCFG_CLKS_28}
-	};
-
-	int nIndexSysClkDiv;
-	int nArraySize =
-	    sizeof(PHYClockDivisors) / sizeof(PHYClockDivisors[0]);
-	unsigned int unClks = NS7520_ETH_MCFG_CLKS_28;	/* defaults to
-							   greatest div */
-
-	DEBUG_FN(DEBUG_INIT);
-
-	for (nIndexSysClkDiv = 0; nIndexSysClkDiv < nArraySize;
-	     nIndexSysClkDiv++) {
-		/* find first sysclock divisor that isn't higher than 2.5 MHz
-		   clock */
-		if (NETARM_XTAL_FREQ /
-		    PHYClockDivisors[nIndexSysClkDiv].unSysClkDivisor <=
-		    unMaxMDIOClk) {
-			unClks = PHYClockDivisors[nIndexSysClkDiv].unClks;
-			break;
-		}
-	}
-
-	DEBUG_ARGS2(DEBUG_INIT,
-		    "Taking MDIO Clock bit mask 0x%0x for max clock %i\n",
-		    unClks, unMaxMDIOClk);
-
-	/* return greatest divisor */
-	return unClks;
-}
-
-/***********************************************************************
- * @Function: ns7520_mii_poll_busy
- * @Return: 0 if timed out otherwise the remaing timeout
- * @Descr: waits until the MII has completed a command or it times out
- *	   code may be interrupted by hard interrupts.
- *	   It is not checked what happens on multiple actions when
- *	   the first is still being busy and we timeout.
- ***********************************************************************/
-
-static unsigned int ns7520_mii_poll_busy(void)
-{
-	unsigned int unTimeout = 1000;
-
-	DEBUG_FN(DEBUG_MII_LOW);
-
-	while (((*get_eth_reg_addr(NS7520_ETH_MIND) & NS7520_ETH_MIND_BUSY)
-		== NS7520_ETH_MIND_BUSY) && unTimeout)
-		unTimeout--;
-
-	return unTimeout;
-}
-
-/* ----------------------------------------------------------------------------
- * Net+ARM ethernet MII functionality.
- */
-#if defined(CONFIG_MII)
-
-/**
- * Maximum MII address we support
- */
-#define MII_ADDRESS_MAX			(31)
-
-/**
- * Maximum MII register address we support
- */
-#define MII_REGISTER_MAX		(31)
-
-/**
- * Ethernet MII interface return values for public functions.
- */
-enum mii_status {
-	MII_STATUS_SUCCESS = 0,
-	MII_STATUS_FAILURE = 1,
-};
-
-/**
- * Read a 16-bit value from an MII register.
- */
-extern int ns7520_miiphy_read(const char *devname, unsigned char const addr,
-		unsigned char const reg, unsigned short *const value)
-{
-	int ret = MII_STATUS_FAILURE;
-
-	/* Parameter checks */
-	if (addr > MII_ADDRESS_MAX) {
-		ERROR(("invalid addr, 0x%02X", addr));
-		goto miiphy_read_failed_0;
-	}
-
-	if (reg > MII_REGISTER_MAX) {
-		ERROR(("invalid reg, 0x%02X", reg));
-		goto miiphy_read_failed_0;
-	}
-
-	if (value == NULL) {
-		ERROR(("NULL value"));
-		goto miiphy_read_failed_0;
-	}
-
-	DEBUG_FN(DEBUG_MII_LOW);
-
-	/* write MII register to be read */
-	*get_eth_reg_addr(NS7520_ETH_MADR) = (addr << 8) | reg;
-
-	*get_eth_reg_addr(NS7520_ETH_MCMD) = NS7520_ETH_MCMD_READ;
-
-	if (!ns7520_mii_poll_busy())
-		printk(KERN_WARNING NS7520_DRIVER_NAME
-		       ": MII still busy in read\n");
-	/* continue to read */
-
-	*get_eth_reg_addr(NS7520_ETH_MCMD) = 0;
-
-	*value = (*get_eth_reg_addr(NS7520_ETH_MRDD));
-	ret = MII_STATUS_SUCCESS;
-	/* Fall through */
-
-      miiphy_read_failed_0:
-	return (ret);
-}
-
-/**
- * Write a 16-bit value to an MII register.
- */
-extern int ns7520_miiphy_write(const char *devname, unsigned char const addr,
-		unsigned char const reg, unsigned short const value)
-{
-	int ret = MII_STATUS_FAILURE;
-
-	/* Parameter checks */
-	if (addr > MII_ADDRESS_MAX) {
-		ERROR(("invalid addr, 0x%02X", addr));
-		goto miiphy_write_failed_0;
-	}
-
-	if (reg > MII_REGISTER_MAX) {
-		ERROR(("invalid reg, 0x%02X", reg));
-		goto miiphy_write_failed_0;
-	}
-
-	/* write MII register to be written */
-	*get_eth_reg_addr(NS7520_ETH_MADR) = (addr << 8) | reg;
-
-	*get_eth_reg_addr(NS7520_ETH_MWTD) = value;
-
-	if (!ns7520_mii_poll_busy()) {
-		printf(KERN_WARNING NS7520_DRIVER_NAME
-		       ": MII still busy in write\n");
-	}
-
-	ret = MII_STATUS_SUCCESS;
-	/* Fall through */
-
-      miiphy_write_failed_0:
-	return (ret);
-}
-#endif				/* defined(CONFIG_MII) */
-
-int ns7520_miiphy_initialize(bd_t *bis)
-{
-#if defined(CONFIG_MII)
-	miiphy_register("ns7520phy", ns7520_miiphy_read, ns7520_miiphy_write);
-#endif
-	return 0;
-}
diff --git a/include/ns7520_eth.h b/include/ns7520_eth.h
deleted file mode 100644
index b509697..0000000
--- a/include/ns7520_eth.h
+++ /dev/null
@@ -1,336 +0,0 @@
-/***********************************************************************
- *
- *  Copyright 2003 by FS Forth-Systeme GmbH.
- *  All rights reserved.
- *
- *  $Id$
- *  @Author: Markus Pietrek
- *  @Descr: Defines the NS7520 ethernet registers.
- *          Stick with the old ETH prefix names instead going to the
- *          new EFE names in the manual.
- *          NS7520_ETH_* refer to NS7520 Hardware
- *           Reference/January 2003 [1]
- *          PHY_LXT971_* refer to Intel LXT971 Datasheet
- *           #249414 Rev. 02 [2]
- *          Partly derived from netarm_eth_module.h
- *
- * Modified by Arthur Shipkowski <art@videon-central.com> from the
- * Linux version to be properly formatted for U-Boot (i.e. no C++ comments)
- *
- ***********************************************************************/
-
-#ifndef FS_NS7520_ETH_H
-#define FS_NS7520_ETH_H
-
-#ifdef CONFIG_DRIVER_NS7520_ETHERNET
-
-#include <miiphy.h>
-#include "lxt971a.h"
-
-/* The port addresses */
-
-#define	NS7520_ETH_MODULE_BASE		(0xFF800000)
-
-#define get_eth_reg_addr(c) \
-     ((volatile unsigned int*) ( NS7520_ETH_MODULE_BASE+(unsigned int) (c)))
-#define NS7520_ETH_EGCR		 (0x0000)	/* Ethernet Gen Control */
-#define NS7520_ETH_EGSR		 (0x0004)	/* Ethernet Gen Status */
-#define NS7520_ETH_FIFO		 (0x0008)	/* FIFO Data */
-#define NS7520_ETH_FIFOL	 (0x000C)	/* FIFO Data Last */
-#define NS7520_ETH_ETSR		 (0x0010)	/* Ethernet Transmit Status */
-#define NS7520_ETH_ERSR		 (0x0014)	/* Ethernet Receive Status */
-#define NS7520_ETH_MAC1		 (0x0400)	/* MAC Config 1 */
-#define NS7520_ETH_MAC2		 (0x0404)	/* MAC Config 2 */
-#define NS7520_ETH_IPGT		 (0x0408)	/* Back2Back InterPacket Gap */
-#define NS7520_ETH_IPGR		 (0x040C)	/* non back2back InterPacket Gap */
-#define NS7520_ETH_CLRT		 (0x0410)	/* Collision Window/Retry */
-#define NS7520_ETH_MAXF		 (0x0414)	/* Maximum Frame Register */
-#define NS7520_ETH_SUPP		 (0x0418)	/* PHY Support */
-#define NS7520_ETH_TEST		 (0x041C)	/* Test Register */
-#define NS7520_ETH_MCFG		 (0x0420)	/* MII Management Configuration */
-#define NS7520_ETH_MCMD		 (0x0424)	/* MII Management Command */
-#define NS7520_ETH_MADR		 (0x0428)	/* MII Management Address */
-#define NS7520_ETH_MWTD		 (0x042C)	/* MII Management Write Data */
-#define NS7520_ETH_MRDD		 (0x0430)	/* MII Management Read Data */
-#define NS7520_ETH_MIND		 (0x0434)	/* MII Management Indicators */
-#define NS7520_ETH_SMII		 (0x0438)	/* SMII Status Register */
-#define NS7520_ETH_SA1		 (0x0440)	/* Station Address 1 */
-#define NS7520_ETH_SA2		 (0x0444)	/* Station Address 2 */
-#define NS7520_ETH_SA3		 (0x0448)	/* Station Address 3 */
-#define NS7520_ETH_SAFR		 (0x05C0)	/* Station Address Filter */
-#define NS7520_ETH_HT1		 (0x05D0)	/* Hash Table 1 */
-#define NS7520_ETH_HT2		 (0x05D4)	/* Hash Table 2 */
-#define NS7520_ETH_HT3		 (0x05D8)	/* Hash Table 3 */
-#define NS7520_ETH_HT4		 (0x05DC)	/* Hash Table 4 */
-
-/* EGCR Ethernet General Control Register Bit Fields*/
-
-#define NS7520_ETH_EGCR_ERX	 (0x80000000)	/* Enable Receive FIFO */
-#define NS7520_ETH_EGCR_ERXDMA	 (0x40000000)	/* Enable Receive DMA */
-#define NS7520_ETH_EGCR_ERXLNG	 (0x20000000)	/* Accept Long packets */
-#define NS7520_ETH_EGCR_ERXSHT	 (0x10000000)	/* Accept Short packets */
-#define NS7520_ETH_EGCR_ERXREG	 (0x08000000)	/* Enable Receive Data Interrupt */
-#define NS7520_ETH_EGCR_ERFIFOH	 (0x04000000)	/* Enable Receive Half-Full Int */
-#define NS7520_ETH_EGCR_ERXBR	 (0x02000000)	/* Enable Receive buffer ready */
-#define NS7520_ETH_EGCR_ERXBAD	 (0x01000000)	/* Accept bad receive packets */
-#define NS7520_ETH_EGCR_ETX	 (0x00800000)	/* Enable Transmit FIFO */
-#define NS7520_ETH_EGCR_ETXDMA	 (0x00400000)	/* Enable Transmit DMA */
-#define NS7520_ETH_EGCR_ETXWM_R  (0x00300000)	/* Enable Transmit FIFO mark Reserv */
-#define NS7520_ETH_EGCR_ETXWM_75 (0x00200000)	/* Enable Transmit FIFO mark 75% */
-#define NS7520_ETH_EGCR_ETXWM_50 (0x00100000)	/* Enable Transmit FIFO mark 50% */
-#define NS7520_ETH_EGCR_ETXWM_25 (0x00000000)	/* Enable Transmit FIFO mark 25% */
-#define NS7520_ETH_EGCR_ETXREG	 (0x00080000)	/* Enable Transmit Data Read Int */
-#define NS7520_ETH_EGCR_ETFIFOH	 (0x00040000)	/* Enable Transmit Fifo Half Int */
-#define NS7520_ETH_EGCR_ETXBC	 (0x00020000)	/* Enable Transmit Buffer Compl Int */
-#define NS7520_ETH_EGCR_EFULLD	 (0x00010000)	/* Enable Full Duplex Operation */
-#define NS7520_ETH_EGCR_MODE_MA  (0x0000C000)	/* Mask */
-#define NS7520_ETH_EGCR_MODE_SEE (0x0000C000)	/* 10 Mbps SEEQ ENDEC PHY */
-#define NS7520_ETH_EGCR_MODE_LEV (0x00008000)	/* 10 Mbps Level1 ENDEC PHY */
-#define NS7520_ETH_EGCR_RES1     (0x00002000)	/* Reserved */
-#define NS7520_ETH_EGCR_RXCINV	 (0x00001000)	/* Invert the receive clock input */
-#define NS7520_ETH_EGCR_TXCINV	 (0x00000800)	/* Invert the transmit clock input */
-#define NS7520_ETH_EGCR_PNA	 (0x00000400)	/* pSOS pNA buffer */
-#define NS7520_ETH_EGCR_MAC_RES	 (0x00000200)	/* MAC Software reset */
-#define NS7520_ETH_EGCR_ITXA	 (0x00000100)	/* Insert Transmit Source Address */
-#define NS7520_ETH_EGCR_ENDEC_MA (0x000000FC)	/* ENDEC media control bits */
-#define NS7520_ETH_EGCR_EXINT_MA (0x00000003)	/* Mask */
-#define NS7520_ETH_EGCR_EXINT_RE (0x00000003)	/* Reserved */
-#define NS7520_ETH_EGCR_EXINT_TP (0x00000002)	/* TP-PMD Mode */
-#define NS7520_ETH_EGCR_EXINT_10 (0x00000001)	/* 10-MBit Mode */
-#define NS7520_ETH_EGCR_EXINT_NO (0x00000000)	/* MII normal operation */
-
-/* EGSR Ethernet General Status Register Bit Fields*/
-
-#define NS7520_ETH_EGSR_RES1	 (0xC0000000)	/* Reserved */
-#define NS7520_ETH_EGSR_RXFDB_MA (0x30000000)	/* Receive FIFO mask */
-#define NS7520_ETH_EGSR_RXFDB_3	 (0x30000000)	/* Receive FIFO 3 bytes available */
-#define NS7520_ETH_EGSR_RXFDB_2	 (0x20000000)	/* Receive FIFO 2 bytes available */
-#define NS7520_ETH_EGCR_RXFDB_1	 (0x10000000)	/* Receive FIFO 1 Bytes available */
-#define NS7520_ETH_EGCR_RXFDB_4	 (0x00000000)	/* Receive FIFO 4 Bytes available */
-#define NS7520_ETH_EGSR_RXREGR	 (0x08000000)	/* Receive Register Ready */
-#define NS7520_ETH_EGSR_RXFIFOH	 (0x04000000)	/* Receive FIFO Half Full */
-#define NS7520_ETH_EGSR_RXBR	 (0x02000000)	/* Receive Buffer Ready */
-#define NS7520_ETH_EGSR_RXSKIP	 (0x01000000)	/* Receive Buffer Skip */
-#define NS7520_ETH_EGSR_RES2	 (0x00F00000)	/* Reserved */
-#define NS7520_ETH_EGSR_TXREGE	 (0x00080000)	/* Transmit Register Empty */
-#define NS7520_ETH_EGSR_TXFIFOH	 (0x00040000)	/* Transmit FIFO half empty */
-#define NS7520_ETH_EGSR_TXBC	 (0x00020000)	/* Transmit buffer complete */
-#define NS7520_ETH_EGSR_TXFIFOE	 (0x00010000)	/* Transmit FIFO empty */
-#define NS7520_ETH_EGSR_RXPINS	 (0x0000FC00)	/* ENDEC Phy Status */
-#define NS7520_ETH_EGSR_RES3	 (0x000003FF)	/* Reserved */
-
-/* ETSR Ethernet Transmit Status Register Bit Fields*/
-
-#define NS7520_ETH_ETSR_RES1	 (0xFFFF0000)	/* Reserved */
-#define NS7520_ETH_ETSR_TXOK	 (0x00008000)	/* Packet transmitted OK */
-#define NS7520_ETH_ETSR_TXBR	 (0x00004000)	/* Broadcast packet transmitted */
-#define NS7520_ETH_ETSR_TXMC	 (0x00002000)	/* Multicast packet transmitted */
-#define NS7520_ETH_ETSR_TXAL	 (0x00001000)	/* Transmit abort - late collision */
-#define NS7520_ETH_ETSR_TXAED	 (0x00000800)	/* Transmit abort - deferral */
-#define NS7520_ETH_ETSR_TXAEC	 (0x00000400)	/* Transmit abort - exc collisions */
-#define NS7520_ETH_ETSR_TXAUR	 (0x00000200)	/* Transmit abort - underrun */
-#define NS7520_ETH_ETSR_TXAJ	 (0x00000100)	/* Transmit abort - jumbo */
-#define NS7520_ETH_ETSR_RES2	 (0x00000080)	/* Reserved */
-#define NS7520_ETH_ETSR_TXDEF	 (0x00000040)	/* Transmit Packet Deferred */
-#define NS7520_ETH_ETSR_TXCRC	 (0x00000020)	/* Transmit CRC error */
-#define NS7520_ETH_ETSR_RES3	 (0x00000010)	/* Reserved */
-#define NS7520_ETH_ETSR_TXCOLC   (0x0000000F)	/* Transmit Collision Count */
-
-/* ERSR Ethernet Receive Status Register Bit Fields*/
-
-#define NS7520_ETH_ERSR_RXSIZE	 (0xFFFF0000)	/* Receive Buffer Size */
-#define NS7520_ETH_ERSR_RXCE	 (0x00008000)	/* Receive Carrier Event */
-#define NS7520_ETH_ERSR_RXDV	 (0x00004000)	/* Receive Data Violation Event */
-#define NS7520_ETH_ERSR_RXOK	 (0x00002000)	/* Receive Packet OK */
-#define NS7520_ETH_ERSR_RXBR	 (0x00001000)	/* Receive Broadcast Packet */
-#define NS7520_ETH_ERSR_RXMC	 (0x00000800)	/* Receive Multicast Packet */
-#define NS7520_ETH_ERSR_RXCRC	 (0x00000400)	/* Receive Packet has CRC error */
-#define NS7520_ETH_ERSR_RXDR	 (0x00000200)	/* Receive Packet has dribble error */
-#define NS7520_ETH_ERSR_RXCV	 (0x00000100)	/* Receive Packet code violation */
-#define NS7520_ETH_ERSR_RXLNG	 (0x00000080)	/* Receive Packet too long */
-#define NS7520_ETH_ERSR_RXSHT	 (0x00000040)	/* Receive Packet too short */
-#define NS7520_ETH_ERSR_ROVER	 (0x00000020)	/* Recive overflow */
-#define NS7520_ETH_ERSR_RES	 (0x0000001F)	/* Reserved */
-
-/* MAC1 MAC Configuration Register 1 Bit Fields*/
-
-#define NS7520_ETH_MAC1_RES1	 (0xFFFF0000)	/* Reserved */
-#define NS7520_ETH_MAC1_SRST	 (0x00008000)	/* Soft Reset */
-#define NS7520_ETH_MAC1_SIMMRST	 (0x00004000)	/* Simulation Reset */
-#define NS7520_ETH_MAC1_RES2	 (0x00003000)	/* Reserved */
-#define NS7520_ETH_MAC1_RPEMCSR	 (0x00000800)	/* Reset PEMCS/RX */
-#define NS7520_ETH_MAC1_RPERFUN	 (0x00000400)	/* Reset PERFUN */
-#define NS7520_ETH_MAC1_RPEMCST	 (0x00000200)	/* Reset PEMCS/TX */
-#define NS7520_ETH_MAC1_RPETFUN	 (0x00000100)	/* Reset PETFUN */
-#define NS7520_ETH_MAC1_RES3	 (0x000000E0)	/* Reserved */
-#define NS7520_ETH_MAC1_LOOPBK	 (0x00000010)	/* Internal Loopback */
-#define NS7520_ETH_MAC1_TXFLOW	 (0x00000008)	/* TX flow control */
-#define NS7520_ETH_MAC1_RXFLOW	 (0x00000004)	/* RX flow control */
-#define NS7520_ETH_MAC1_PALLRX	 (0x00000002)	/* Pass ALL receive frames */
-#define NS7520_ETH_MAC1_RXEN	 (0x00000001)	/* Receive enable */
-
-/* MAC Configuration Register 2 Bit Fields*/
-
-#define NS7520_ETH_MAC2_RES1	 (0xFFFF8000)	/* Reserved */
-#define NS7520_ETH_MAC2_EDEFER	 (0x00004000)	/* Excess Deferral */
-#define NS7520_ETH_MAC2_BACKP	 (0x00002000)	/* Backpressure/NO back off */
-#define NS7520_ETH_MAC2_NOBO	 (0x00001000)	/* No back off */
-#define NS7520_ETH_MAC2_RES2	 (0x00000C00)	/* Reserved */
-#define NS7520_ETH_MAC2_LONGP	 (0x00000200)	/* Long Preable enforcement */
-#define NS7520_ETH_MAC2_PUREP	 (0x00000100)	/* Pure preamble enforcement */
-#define NS7520_ETH_MAC2_AUTOP	 (0x00000080)	/* Auto detect PAD enable */
-#define NS7520_ETH_MAC2_VLANP	 (0x00000040)	/* VLAN pad enable */
-#define NS7520_ETH_MAC2_PADEN	 (0x00000020)	/* PAD/CRC enable */
-#define NS7520_ETH_MAC2_CRCEN	 (0x00000010)	/* CRC enable */
-#define NS7520_ETH_MAC2_DELCRC	 (0x00000008)	/* Delayed CRC */
-#define NS7520_ETH_MAC2_HUGE	 (0x00000004)	/* Huge frame enable */
-#define NS7520_ETH_MAC2_FLENC	 (0x00000002)	/* Frame length checking */
-#define NS7520_ETH_MAC2_FULLD	 (0x00000001)	/* Full duplex */
-
-/* IPGT Back-to-Back Inter-Packet-Gap Register Bit Fields*/
-
-#define NS7520_ETH_IPGT_RES	 (0xFFFFFF80)	/* Reserved */
-#define NS7520_ETH_IPGT_IPGT	 (0x0000007F)	/* Back-to-Back Interpacket Gap */
-
-/* IPGR Non Back-to-Back Inter-Packet-Gap Register Bit Fields*/
-
-#define NS7520_ETH_IPGR_RES1	 (0xFFFF8000)	/* Reserved */
-#define NS7520_ETH_IPGR_IPGR1	 (0x00007F00)	/* Non Back-to-back Interpacket Gap */
-#define NS7520_ETH_IPGR_RES2	 (0x00000080)	/* Reserved */
-#define NS7520_ETH_IPGR_IPGR2	 (0x0000007F)	/* Non back-to-back Interpacket Gap */
-
-/* CLRT Collision Windows/Collision Retry Register Bit Fields*/
-
-#define NS7520_ETH_CLRT_RES1	 (0xFFFFC000)	/* Reserved */
-#define NS7520_ETH_CLRT_CWIN	 (0x00003F00)	/* Collision Windows */
-#define NS7520_ETH_CLRT_RES2	 (0x000000F0)	/* Reserved */
-#define	NS7520_ETH_CLRT_RETX	 (0x0000000F)	/* Retransmission maximum */
-
-/* MAXF Maximum Frame Register Bit Fields*/
-
-#define NS7520_ETH_MAXF_RES1	 (0xFFFF0000)	/* Reserved */
-#define NS7520_ETH_MAXF_MAXF	 (0x0000FFFF)	/* Maximum frame length */
-
-/* SUPP PHY Support Register Bit Fields*/
-
-#define NS7520_ETH_SUPP_RES1	 (0xFFFFFF00)	/* Reserved */
-#define NS7520_ETH_SUPP_RPE100X	 (0x00000080)	/* Reset PE100X module */
-#define NS7520_ETH_SUPP_FORCEQ	 (0x00000040)	/* Force Quit */
-#define NS7520_ETH_SUPP_NOCIPH	 (0x00000020)	/* No Cipher */
-#define NS7520_ETH_SUPP_DLINKF	 (0x00000010)	/* Disable link fail */
-#define NS7520_ETH_SUPP_RPE10T	 (0x00000008)	/* Reset PE10T module */
-#define NS7520_ETH_SUPP_RES2	 (0x00000004)	/* Reserved */
-#define NS7520_ETH_SUPP_JABBER	 (0x00000002)	/* Enable Jabber protection */
-#define NS7520_ETH_SUPP_BITMODE	 (0x00000001)	/* Bit Mode */
-
-/* TEST Register Bit Fields*/
-
-#define NS7520_ETH_TEST_RES1	 (0xFFFFFFF8)	/* Reserved */
-#define NS7520_ETH_TEST_TBACK	 (0x00000004)	/* Test backpressure */
-#define NS7520_ETH_TEST_TPAUSE	 (0x00000002)	/* Test Pause */
-#define NS7520_ETH_TEST_SPQ	 (0x00000001)	/* Shortcut pause quanta */
-
-/* MCFG MII Management Configuration Register Bit Fields*/
-
-#define NS7520_ETH_MCFG_RES1	 (0xFFFF0000)	/* Reserved */
-#define NS7520_ETH_MCFG_RMIIM	 (0x00008000)	/* Reset MII management */
-#define NS7520_ETH_MCFG_RES2	 (0x00007FE0)	/* Reserved */
-#define NS7520_ETH_MCFG_CLKS_MA	 (0x0000001C)	/* Clock Select */
-#define NS7520_ETH_MCFG_CLKS_4	 (0x00000004)	/* Sysclk / 4 */
-#define NS7520_ETH_MCFG_CLKS_6	 (0x00000008)	/* Sysclk / 6 */
-#define NS7520_ETH_MCFG_CLKS_8	 (0x0000000C)	/* Sysclk / 8 */
-#define NS7520_ETH_MCFG_CLKS_10	 (0x00000010)	/* Sysclk / 10 */
-#define NS7520_ETH_MCFG_CLKS_14	 (0x00000014)	/* Sysclk / 14 */
-#define NS7520_ETH_MCFG_CLKS_20	 (0x00000018)	/* Sysclk / 20 */
-#define NS7520_ETH_MCFG_CLKS_28	 (0x0000001C)	/* Sysclk / 28 */
-#define NS7520_ETH_MCFG_SPRE	 (0x00000002)	/* Suppress preamble */
-#define NS7520_ETH_MCFG_SCANI	 (0x00000001)	/* Scan increment */
-
-/* MCMD MII Management Command Register Bit Fields*/
-
-#define NS7520_ETH_MCMD_RES1	 (0xFFFFFFFC)	/* Reserved */
-#define NS7520_ETH_MCMD_SCAN	 (0x00000002)	/* Automatically Scan for Read Data */
-#define NS7520_ETH_MCMD_READ	 (0x00000001)	/* Single scan for Read Data */
-
-/* MCMD MII Management Address Register Bit Fields*/
-
-#define NS7520_ETH_MADR_RES1	 (0xFFFFE000)	/* Reserved */
-#define NS7520_ETH_MADR_DADR	 (0x00001F00)	/* MII PHY device address */
-#define NS7520_ETH_MADR_RES2	 (0x000000E0)	/* Reserved */
-#define NS7520_ETH_MADR_RADR	 (0x0000001F)	/* MII PHY register address */
-
-/* MWTD MII Management Write Data Register Bit Fields*/
-
-#define NS7520_ETH_MWTD_RES1	 (0xFFFF0000)	/* Reserved */
-#define NS7520_ETH_MWTD_MWTD	 (0x0000FFFF)	/* MII Write Data */
-
-/* MRRD MII Management Read Data Register Bit Fields*/
-
-#define NS7520_ETH_MRRD_RES1	 (0xFFFF0000)	/* Reserved */
-#define NS7520_ETH_MRRD_MRDD	 (0x0000FFFF)	/* MII Read Data */
-
-/* MIND MII Management Indicators Register Bit Fields*/
-
-#define NS7520_ETH_MIND_RES1	 (0xFFFFFFF8)	/* Reserved */
-#define NS7520_ETH_MIND_NVALID	 (0x00000004)	/* Read Data not valid */
-#define NS7520_ETH_MIND_SCAN	 (0x00000002)	/* Automatically scan for read data */
-#define NS7520_ETH_MIND_BUSY	 (0x00000001)	/* MII interface busy */
-
-/* SMII Status Register Bit Fields*/
-
-#define NS7520_ETH_SMII_RES1	 (0xFFFFFFE0)	/* Reserved */
-#define NS7520_ETH_SMII_CLASH	 (0x00000010)	/* MAC-to-MAC with PHY */
-#define NS7520_ETH_SMII_JABBER	 (0x00000008)	/* Jabber condition present */
-#define NS7520_ETH_SMII_LINK	 (0x00000004)	/* Link OK */
-#define NS7520_ETH_SMII_DUPLEX	 (0x00000002)	/* Full-duplex operation */
-#define NS7520_ETH_SMII_SPEED	 (0x00000001)	/* 100 Mbps */
-
-/* SA1 Station Address 1 Register Bit Fields*/
-
-#define NS7520_ETH_SA1_RES1	 (0xFFFF0000)	/* Reserved */
-#define NS7520_ETH_SA1_OCTET1	 (0x0000FF00)	/* Station Address octet 1 */
-#define NS7520_ETH_SA1_OCTET2	 (0x000000FF)	/* Station Address octet 2 */
-
-/* SA2 Station Address 2 Register Bit Fields*/
-
-#define NS7520_ETH_SA2_RES1	 (0xFFFF0000)	/* Reserved */
-#define NS7520_ETH_SA2_OCTET3	 (0x0000FF00)	/* Station Address octet 3 */
-#define NS7520_ETH_SA2_OCTET4	 (0x000000FF)	/* Station Address octet 4 */
-
-/* SA3 Station Address 3 Register Bit Fields*/
-
-#define NS7520_ETH_SA3_RES1	 (0xFFFF0000)	/* Reserved */
-#define NS7520_ETH_SA3_OCTET5	 (0x0000FF00)	/* Station Address octet 5 */
-#define NS7520_ETH_SA3_OCTET6	 (0x000000FF)	/* Station Address octet 6 */
-
-/* SAFR Station Address Filter Register Bit Fields*/
-
-#define NS7520_ETH_SAFR_RES1	 (0xFFFFFFF0)	/* Reserved */
-#define NS7520_ETH_SAFR_PRO	 (0x00000008)	/* Enable Promiscuous mode */
-#define NS7520_ETH_SAFR_PRM	 (0x00000004)	/* Accept ALL multicast packets */
-#define NS7520_ETH_SAFR_PRA	 (0x00000002)	/* Accept multicast packets table */
-#define NS7520_ETH_SAFR_BROAD	 (0x00000001)	/* Accept ALL Broadcast packets */
-
-/* HT1 Hash Table 1 Register Bit Fields*/
-
-#define NS7520_ETH_HT1_RES1	 (0xFFFF0000)	/* Reserved */
-#define NS7520_ETH_HT1_HT1	 (0x0000FFFF)	/* CRC value 15-0 */
-
-/* HT2 Hash Table 2 Register Bit Fields*/
-
-#define NS7520_ETH_HT2_RES1	 (0xFFFF0000)	/* Reserved */
-#define NS7520_ETH_HT2_HT2	 (0x0000FFFF)	/* CRC value 31-16 */
-
-/* HT3 Hash Table 3 Register Bit Fields*/
-
-#define NS7520_ETH_HT3_RES1	 (0xFFFF0000)	/* Reserved */
-#define NS7520_ETH_HT3_HT3	 (0x0000FFFF)	/* CRC value 47-32 */
-
-/* HT4 Hash Table 4 Register Bit Fields*/
-
-#define NS7520_ETH_HT4_RES1	 (0xFFFF0000)	/* Reserved */
-#define NS7520_ETH_HT4_HT4	 (0x0000FFFF)	/* CRC value 63-48 */
-
-#endif				/* CONFIG_DRIVER_NS7520_ETHERNET */
-
-#endif				/* FS_NS7520_ETH_H */
diff --git a/net/eth.c b/net/eth.c
index 1c0c780..fba3c1f 100644
--- a/net/eth.c
+++ b/net/eth.c
@@ -541,7 +541,6 @@ char *eth_get_name (void)
 #warning Ethernet driver is deprecated.  Please update to use CONFIG_NET_MULTI
 
 extern int mcf52x2_miiphy_initialize(bd_t *bis);
-extern int ns7520_miiphy_initialize(bd_t *bis);
 
 
 int eth_initialize(bd_t *bis)
@@ -553,9 +552,6 @@ int eth_initialize(bd_t *bis)
 #if defined(CONFIG_MCF52x2)
 	mcf52x2_miiphy_initialize(bis);
 #endif
-#if defined(CONFIG_DRIVER_NS7520_ETHERNET)
-	ns7520_miiphy_initialize(bis);
-#endif
 	return 0;
 }
 #endif
