diff --git a/MAINTAINERS b/MAINTAINERS
index c10996c..db7d85a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -853,6 +853,7 @@ Marek Vasut <marek.vasut@gmail.com>
 	zipitz2		xscale/pxa
  	efikamx		i.MX51
 	efikasb		i.MX51
+	colibri_t20	Tegra2 (ARM7 & A9 Dual Core)
 
 Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
 
diff --git a/board/toradex/colibri_t20/Makefile b/board/toradex/colibri_t20/Makefile
new file mode 100644
index 0000000..5002dd5
--- /dev/null
+++ b/board/toradex/colibri_t20/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= colibri_t20.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/toradex/colibri_t20/colibri_t20.c b/board/toradex/colibri_t20/colibri_t20.c
new file mode 100644
index 0000000..4945888
--- /dev/null
+++ b/board/toradex/colibri_t20/colibri_t20.c
@@ -0,0 +1,119 @@
+/*
+ * Toradex Colibri T20 Board Support
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * Based on code:
+ *
+ * Copyright (C) 2011 Ant Micro <www.antmicro.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <asm/io.h>
+#include <asm/arch/tegra2.h>
+#include <asm/arch/sys_proto.h>
+
+#include <asm/arch/clk_rst.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/uart.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const struct tegra2_sysinfo sysinfo = {
+	CONFIG_TEGRA2_BOARD_STRING
+};
+
+int timer_init(void)
+{
+	return 0;
+}
+
+static void uart_init(void)
+{
+	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	struct clk_pll *pll = &clkrst->crc_pll[CLOCK_PLL_ID_PERIPH];
+	uint32_t reg;
+
+	reg = readl(&pll->pll_base);
+	if (!(reg & PLL_BASE_OVRRIDE_MASK)) {
+		/* Override pllp setup for 216MHz operation. */
+		reg = PLL_BYPASS_MASK | PLL_BASE_OVRRIDE_MASK |
+			(1 << PLL_DIVP_SHIFT) | (0xd << PLL_DIVM_SHIFT);
+		reg |= (NVRM_PLLP_FIXED_FREQ_KHZ / 500) << PLL_DIVN_SHIFT;
+		writel(reg, &pll->pll_base);
+
+		reg |= PLL_ENABLE_MASK;
+		writel(reg, &pll->pll_base);
+
+		reg &= ~PLL_BYPASS_MASK;
+		writel(reg, &pll->pll_base);
+	}
+
+#ifdef	CONFIG_TEGRA2_ENABLE_UARTA
+	/* Assert UART reset and enable clock */
+	reset_set_enable(PERIPH_ID_UART1, 1);
+	clock_enable(PERIPH_ID_UART1);
+
+	/* Enable pllp_out0 to UART */
+	clrbits_le32(&clkrst->crc_clk_src_uarta, 3 << 30);
+
+	/* wait for 2us */
+	udelay(2);
+
+	/* De-assert reset to UART */
+	reset_set_enable(PERIPH_ID_UART1, 0);
+#endif
+}
+
+static void pinmux_init(void)
+{
+	struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+
+	/* SDIO 1 */
+	clrbits_le32(&pmt->pmt_tri[TRISTATE_REG(PIN_ATA)], 1 << 30);
+
+	/* Mux SDB/SDC to PWM */
+	clrsetbits_le32(&pmt->pmt_ctl_d, 0xcc00, 0x4400);
+
+	/* Mux SDIO1 to UARTA */
+	setbits_le32(&pmt->pmt_ctl_a, 3 << 30);
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+extern int tegra2_start(void);
+int board_early_init_f(void)
+{
+	pinmux_init();
+	uart_init();
+	tegra2_start();
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	gd->bd->bi_boot_params = NV_PA_SDRAM_BASE + 0x100;
+	return 0;
+}
diff --git a/boards.cfg b/boards.cfg
index c485cd7..6cc2855 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -188,6 +188,7 @@ s5pc210_universal            arm         armv7       universal_c210      samsung
 smdkv310		     arm	 armv7	     smdkv310		 samsung	s5pc2xx
 harmony                      arm         armv7       harmony             nvidia         tegra2
 seaboard                     arm         armv7       seaboard            nvidia         tegra2
+colibri_t20		     arm	 armv7	     colibri_t20	 toradex	tegra2	
 u8500_href                   arm         armv7       u8500               st-ericsson    u8500
 actux1_4_16                  arm         ixp         actux1              -              -           actux1:FLASH2X2
 actux1_8_16                  arm         ixp         actux1              -              -           actux1:FLASH1X8
diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h
new file mode 100644
index 0000000..8fc0898
--- /dev/null
+++ b/include/configs/colibri_t20.h
@@ -0,0 +1,162 @@
+/*
+ * Toradex Colibri T20 Configuration File
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * Based on code:
+ *
+ * Copyright (C) 2011 Ant Micro <www.antmicro.com>
+ * Copyright (C) 2010, 2011 NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef	__CONFIG_H
+#define	__CONFIG_H
+
+#include <asm/sizes.h>
+#include <asm/arch/tegra2.h>
+
+/*
+ * High Level Configuration Options
+ */
+#define	CONFIG_ARMCORTEXA9		/* This is an ARM V7 CPU core */
+#define	CONFIG_TEGRA2			/* in a NVidia Tegra2 core */
+#define	CONFIG_MACH_TEGRA_GENERIC	/* which is a Tegra generic machine */
+#define	CONFIG_SYS_L2CACHE_OFF		/* No L2 cache */
+
+#define	CONFIG_ENABLE_CORTEXA9		/* enable CPU (A9 complex) */
+
+/*
+ * Board-specific config
+ */
+#define	CONFIG_SYS_BOARD_ODMDATA	0x100d8011 /* lp1, 256MB */
+#define	CONFIG_SYS_CPU_OSC_FREQUENCY	1000000	/* Set CPU clock to 1GHz */
+#define	CONFIG_SYS_TEGRA2_XTAL_MHZ	13
+
+#define	CONFIG_BOARD_EARLY_INIT_F
+#define	CONFIG_MACH_TYPE		MACH_TYPE_COLIBRI_TEGRA2
+#define	CONFIG_ENV_IS_NOWHERE
+#define	CONFIG_ENV_SIZE			0x20000
+#define	CONFIG_ENV_OVERWRITE
+
+#define	CONFIG_TEGRA2_BOARD_STRING	"TORADEX Colibri T20"
+
+/*
+ * Display CPU and Board information
+ */
+#define	CONFIG_DISPLAY_CPUINFO
+#define	CONFIG_DISPLAY_BOARDINFO
+
+#define	CONFIG_SKIP_LOWLEVEL_INIT
+
+#define	CONFIG_CMDLINE_TAG
+#define	CONFIG_OF_LIBFDT
+
+#define	CONFIG_BOOTDELAY		3
+
+#define	CONFIG_SYS_MALLOC_LEN		(4 << 20)
+
+/*
+ * Default commands
+ */
+#include <config_cmd_default.h>
+#undef	CONFIG_CMD_FLASH
+#undef	CONFIG_CMD_FPGA
+#undef	CONFIG_CMD_IMI
+#undef	CONFIG_CMD_IMLS
+#undef	CONFIG_CMD_NFS
+#define	CONFIG_CMD_GPIO
+#define	CONFIG_NET_MULTI
+
+/*
+ * Command line setup
+ */
+#define	CONFIG_CMDLINE_EDITING
+#define	CONFIG_COMMAND_HISTORY
+#define	CONFIG_AUTOCOMPLETE
+
+#define	CONFIG_SYS_NO_FLASH
+
+/*
+ * Environment information
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS \
+	"console=ttyS0,115200n8\0" \
+	"mem=256M@0x0\0" \
+	"smpflag=smp\0" \
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define	CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define	CONFIG_SYS_PROMPT		"=> "
+/*
+ * Increasing the size of the IO buffer as default nfsargs size is more
+ *  than 256 and so it is not possible to edit it
+ */
+#define	CONFIG_SYS_CBSIZE		(256 * 2) /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define	CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define	CONFIG_SYS_MAXARGS		16	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define	CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+
+/*
+ * Physical Memory Map
+ */
+#define	CONFIG_NR_DRAM_BANKS		1
+#define	PHYS_SDRAM_1			TEGRA2_SDRC_CS0
+#define	PHYS_SDRAM_1_SIZE		0x10000000	/* 256 MB */
+#define	CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+#define	CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM_1 + 0x600000)
+#define	CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x100000)
+
+#define	CONFIG_SYS_LOAD_ADDR		0xA00800
+#define	CONFIG_SYS_TEXT_BASE		0x108000
+
+#define	CONFIG_SYS_HZ			1000
+#define	CONFIG_SYS_INIT_SP_ADDR		0x80000
+
+#define	CONFIG_LOADADDR			0x408000
+
+/*
+ * GPIO
+ */
+#define	CONFIG_TEGRA2_GPIO
+
+/*
+ * UART
+ */
+#define	CONFIG_SERIAL_MULTI
+#define	CONFIG_TEGRA2_ENABLE_UARTA
+#define	CONFIG_SYS_NS16550
+#define	CONFIG_SYS_NS16550_SERIAL
+#define	CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define	CONFIG_SYS_NS16550_CLK		216000000
+#define	CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
+#define	CONFIG_CONS_INDEX		1
+#define	CONFIG_BAUDRATE			115200
+#define	CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#endif	/* __CONFIG_H */
