new file mode 100644
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak *~ .depend
+
+#########################################################################
+# This is for $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
new file mode 100644
@@ -0,0 +1,570 @@
+/*
+ * (C) Copyright 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Based on da830evm.c. Original Copyrights follow:
+ *
+ * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <environment.h>
+#include <hwconfig.h>
+#include <i2c.h>
+#include <malloc.h>
+#include <miiphy.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/emif_defs.h>
+#include <asm/arch/emac_defs.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/davinci_misc.h>
+#include <asm/arch/timer_defs.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct lpsc_resource lpsc[] = {
+ { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
+ { DAVINCI_LPSC_EMAC }, /* image download */
+ { DAVINCI_LPSC_UART2 }, /* console */
+ { DAVINCI_LPSC_GPIO },
+};
+
+/* missing functions from board/davinci/common/misc.c */
+#ifndef CONFIG_USE_IRQ
+void irq_init(void)
+{
+ /*
+ * Mask all IRQs by clearing the global enable and setting
+ * the enable clear for all the 90 interrupts.
+ */
+
+ writel(0, &davinci_aintc_regs->ger);
+
+ writel(0, &davinci_aintc_regs->hier);
+
+ writel(0xffffffff, &davinci_aintc_regs->ecr1);
+ writel(0xffffffff, &davinci_aintc_regs->ecr2);
+ writel(0xffffffff, &davinci_aintc_regs->ecr3);
+}
+#endif
+
+void davinci_emac_mii_mode_sel(int mode_sel)
+{
+ int val;
+
+ val = readl(&davinci_syscfg_regs->cfgchip3);
+ if (mode_sel == 0)
+ val &= ~(1 << 8);
+ else
+ val |= (1 << 8);
+ writel(val, &davinci_syscfg_regs->cfgchip3);
+}
+
+int da8xx_configure_lpsc_items(const struct lpsc_resource *item,
+ const int n_items)
+{
+ int i;
+
+ for (i = 0; i < n_items; i++)
+ lpsc_on(item[i].lpsc_no);
+
+ return 0;
+}
+
+int davinci_configure_pin_mux_items(const struct pinmux_resource *item,
+ const int n_items)
+{
+ return 0;
+}
+
+static void enbw_cmc_switch(int port, int on)
+{
+ const char *devname;
+ unsigned char phyaddr = 3;
+ unsigned char reg = 0;
+ unsigned short data;
+
+ if (port == 1)
+ phyaddr = 2;
+
+ devname = miiphy_get_current_dev();
+ if (!devname) {
+ printf("Error: no mii device\n");
+ return;
+ }
+ if (miiphy_read(devname, phyaddr, reg, &data) != 0) {
+ printf("Error reading from the PHY addr=%02x reg=%02x\n",
+ phyaddr, reg);
+ return;
+ }
+ if (on)
+ data &= ~0x0800;
+ else
+ data |= 0x0800;
+
+ if (miiphy_write(devname, phyaddr, reg, data) != 0) {
+ printf("Error writing to the PHY addr=%02x reg=%02x\n",
+ phyaddr, reg);
+ return;
+ }
+}
+
+int board_init(void)
+{
+#ifndef CONFIG_USE_IRQ
+ irq_init();
+#endif
+ /* address of boot parameters, not used as booting with DTT */
+ gd->bd->bi_boot_params = 0;
+
+ /*
+ * Power on required peripherals
+ * ARM does not have access by default to PSC0 and PSC1
+ * assuming here that the DSP bootloader has set the IOPU
+ * such that PSC access is available to ARM
+ */
+ if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
+ return 1;
+
+ /* setup the SUSPSRC for ARM to control emulation suspend */
+ clrbits_le32(&davinci_syscfg_regs->suspsrc,
+ (DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
+ DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
+ DAVINCI_SYSCFG_SUSPSRC_UART2));
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+ davinci_emac_mii_mode_sel(0);
+#endif /* CONFIG_DRIVER_TI_EMAC */
+
+ /* enable the console UART */
+ writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
+ DAVINCI_UART_PWREMU_MGMT_UTRST),
+ &davinci_uart2_ctrl_regs->pwremu_mgmt);
+
+ return 0;
+}
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+/*
+ * Initializes on-board ethernet controllers.
+ */
+int board_eth_init(bd_t *bis)
+{
+ if (!davinci_emac_initialize()) {
+ printf("Error: Ethernet init failed!\n");
+ return -1;
+ }
+
+ if (hwconfig_subarg_cmp("switch", "lan", "on"))
+ /* Switch port lan on */
+ enbw_cmc_switch(1, 1);
+ else
+ enbw_cmc_switch(1, 0);
+
+ if (hwconfig_subarg_cmp("switch", "pwl", "on"))
+ /* Switch port pwl on */
+ enbw_cmc_switch(2, 1);
+ else
+ enbw_cmc_switch(2, 0);
+
+ return 0;
+}
+#endif /* CONFIG_DRIVER_TI_EMAC */
+
+int dram_init(void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size(
+ (long *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_MAX_RAM_BANK_SIZE);
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+}
+
+#ifdef CONFIG_PREBOOT
+static uchar kbd_magic_prefix[] = "key_magic_";
+static uchar kbd_command_prefix[] = "key_cmd_";
+
+struct kbd_data_t {
+ char s1;
+};
+
+struct kbd_data_t *get_keys(struct kbd_data_t *kbd_data)
+{
+ struct davinci_gpio *gpio = davinci_gpio_bank01;
+ unsigned long reg;
+
+ /* read SW1 + SW2 */
+ reg = readl(&gpio->in_data);
+ kbd_data->s1 = ((reg & 0x00003000) >> 12);
+ return kbd_data;
+}
+
+static int compare_magic(const struct kbd_data_t *kbd_data, char *str)
+{
+ char s1 = str[0];
+
+ if (s1 >= '0' && s1 <= '9')
+ s1 -= '0';
+ else if (s1 >= 'a' && s1 <= 'f')
+ s1 = s1 - 'a' + 10;
+ else if (s1 >= 'A' && s1 <= 'F')
+ s1 = s1 - 'A' + 10;
+ else
+ return -1;
+
+ if (s1 != kbd_data->s1)
+ return -1;
+
+ return 0;
+}
+
+static char *key_match(const struct kbd_data_t *kbd_data)
+{
+ char magic[sizeof(kbd_magic_prefix) + 1];
+ char *suffix;
+ char *kbd_magic_keys;
+
+ /*
+ * The following string defines the characters that can be appended
+ * to "key_magic" to form the names of environment variables that
+ * hold "magic" key codes, i. e. such key codes that can cause
+ * pre-boot actions. If the string is empty (""), then only
+ * "key_magic" is checked (old behaviour); the string "125" causes
+ * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
+ */
+ kbd_magic_keys = getenv("magic_keys");
+ if (kbd_magic_keys == NULL)
+ kbd_magic_keys = "";
+
+ /* loop over all magic keys;
+ * use '\0' suffix in case of empty string
+ */
+ for (suffix = kbd_magic_keys; *suffix ||
+ suffix == kbd_magic_keys; ++suffix) {
+ sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
+
+ if (compare_magic(kbd_data, getenv(magic)) == 0) {
+ char cmd_name[sizeof(kbd_command_prefix) + 1];
+ char *cmd;
+
+ sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
+ cmd = getenv(cmd_name);
+
+ return cmd;
+ }
+ }
+
+ return NULL;
+}
+#endif /* CONFIG_PREBOOT */
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_PREBOOT
+ struct kbd_data_t kbd_data;
+ /* Decode keys */
+ char *str = strdup(key_match(get_keys(&kbd_data)));
+ /* Set or delete definition */
+ setenv("preboot", str);
+ free(str);
+#endif /* CONFIG_PREBOOT */
+
+#ifdef CONFIG_HW_WATCHDOG
+ davinci_hw_watchdog_enable();
+#endif
+
+ return 0;
+}
+
+struct cmc_led {
+ char name[20];
+ struct davinci_gpio *gpio;
+ unsigned long mask;
+};
+
+struct cmc_led led_table[] = {
+ {"led1", davinci_gpio_bank01, 0x80000000},
+ {"led2", davinci_gpio_bank01, 0x00000002},
+ {"led3", davinci_gpio_bank01, 0x00000004},
+ {"led4", davinci_gpio_bank01, 0x00000008},
+ {"led5", davinci_gpio_bank01, 0x00000010},
+ {"led6", davinci_gpio_bank01, 0x00000020},
+ {"led7", davinci_gpio_bank01, 0x00000040},
+ {"led8", davinci_gpio_bank01, 0x00004000},
+};
+
+static int cmc_get_led_state(struct cmc_led *led)
+{
+ struct davinci_gpio *gpio = led->gpio;
+ unsigned long reg;
+
+ /* read SW1 + SW2 */
+ reg = readl(&gpio->in_data);
+ if ((reg & led->mask) == led->mask)
+ return 1;
+
+ return 0;
+}
+
+static int cmc_set_led_state(struct cmc_led *led, int state)
+{
+ struct davinci_gpio *gpio = led->gpio;
+ unsigned long reg;
+
+ reg = readl(&gpio->out_data);
+ if (state)
+ reg |= led->mask;
+ else
+ reg &= ~led->mask;
+
+ writel(reg, &gpio->out_data);
+ return 0;
+}
+
+static int do_led(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ struct cmc_led *led;
+ int found = 0;
+ int i = 0;
+ int only_print = 0;
+ int len = ARRAY_SIZE(led_table);
+
+ if (argc < 2)
+ return cmd_usage(cmdtp);
+
+ if (argc < 3)
+ only_print = 1;
+
+ led = led_table;
+ while ((!found) && (i < len)) {
+ if (strcmp(argv[1], led->name) == 0) {
+ found = 1;
+ } else {
+ led++;
+ i++;
+ }
+ }
+ if (!found)
+ return cmd_usage(cmdtp);
+
+ if (only_print) {
+ if (cmc_get_led_state(led))
+ printf("on\n");
+ else
+ printf("off\n");
+
+ return 0;
+ }
+ if (strcmp(argv[2], "on") == 0)
+ cmc_set_led_state(led, 1);
+ else
+ cmc_set_led_state(led, 0);
+
+ return 0;
+}
+
+U_BOOT_CMD(led, 3, 1, do_led,
+ "switch on/off board led",
+ "[name] [on/off]"
+);
+
+#ifdef CONFIG_HW_WATCHDOG
+void hw_watchdog_reset(void)
+{
+ davinci_hw_watchdog_reset();
+}
+#endif
+
+#if defined(CONFIG_POST)
+void arch_memory_failure_handle(void)
+{
+ int state = 1;
+
+ printf("%s: blinking with LEDs\n", __func__);
+ while (1) {
+ cmc_set_led_state(&led_table[0], state);
+ cmc_set_led_state(&led_table[1], state);
+ cmc_set_led_state(&led_table[2], state);
+ if (state)
+ state = 0;
+ else
+ state = 1;
+ udelay(500);
+ }
+}
+#endif
+
+#if defined(CONFIG_BOOTCOUNT_LIMIT)
+void bootcount_store(ulong a)
+{
+ void *reg = (void *)CONFIG_SYS_BOOTCOUNT_ADDR;
+
+ /*
+ * write RTC kick register to enable write
+ * for RTC Scratch registers. Cratch0 and 1 are
+ * used for bootcount values.
+ */
+ out_be32(reg + 0x0c, 0x130be783);
+ out_be32(reg + 0x10, 0xe0f1a495);
+ out_be32(reg, a);
+ out_be32(reg + 4, BOOTCOUNT_MAGIC);
+}
+
+ulong bootcount_load(void)
+{
+ void *reg = (void *)CONFIG_SYS_BOOTCOUNT_ADDR;
+
+ if (in_be32(reg + 4) != BOOTCOUNT_MAGIC)
+ return 0;
+ else
+ return in_be32(reg);
+}
+#endif
+
+void board_gpio_init(void)
+{
+ struct davinci_gpio *gpio = davinci_gpio_bank8;
+
+ /*
+ * Counter IF: RS485 enable, low enable
+ * GP8[11] = Out[9] set to output and state 0
+ */
+ clrbits_le32(&gpio->dir, 0x00000800);
+ clrbits_le32(&gpio->out_data, 0x00000800);
+ /*
+ * Counter IF: Isolation RS485
+ * GP8[10] = Out[10] set to output and state 0
+ */
+ clrbits_le32(&gpio->dir, 0x00000400);
+ clrbits_le32(&gpio->out_data, 0x00000400);
+ /*
+ * W2HUT: RS485 Rx enable:
+ * GP8[9] = Out[11] set to output and state 0
+ */
+ clrbits_le32(&gpio->dir, 0x00000200);
+ clrbits_le32(&gpio->out_data, 0x00000200);
+ /*
+ * W2HUT: Isolation RS485:
+ * GP8[8] = Out[12] set to output and state 0
+ */
+ clrbits_le32(&gpio->dir, 0x00000100);
+ clrbits_le32(&gpio->out_data, 0x00000100);
+
+ gpio = davinci_gpio_bank67;
+ /*
+ * SW Reset 4 port LAN switch
+ * GP7[15] = Out[4] set to output state 1
+ */
+ clrbits_le32(&gpio->dir, 0x80000000);
+ setbits_le32(&gpio->out_data, 0x80000000);
+ /*
+ * Enable 11V PLC Vaa, high active
+ * GP7[14] = Out[3] set to output state 0
+ */
+ clrbits_le32(&gpio->dir, 0x40000000);
+ clrbits_le32(&gpio->out_data, 0x40000000);
+ /*
+ * Enable 1.5V PLC Core, high active
+ * GP7[13] = Out[2] set to output state 0
+ */
+ clrbits_le32(&gpio->dir, 0x20000000);
+ clrbits_le32(&gpio->out_data, 0x20000000);
+ /*
+ * Disable USB0 VBUS, low active
+ * GP7[12] = Out[2] set to output state 1
+ */
+ clrbits_le32(&gpio->dir, 0x10000000);
+ setbits_le32(&gpio->out_data, 0x10000000);
+ /*
+ * SW_reset for PLC modul, low active
+ * GP6[13] = Out[5] set to output state 1
+ */
+ clrbits_le32(&gpio->dir, 0x00002000);
+ setbits_le32(&gpio->out_data, 0x00002000);
+ /*
+ * LCM Bus Signal RS; R/W and E
+ * GP6[12..11] = Out[6..7]
+ */
+ clrbits_le32(&gpio->dir, 0x00001800);
+ clrbits_le32(&gpio->out_data, 0x00001800);
+ /*
+ * Pairing-button for PLC Modul = Out[18]
+ */
+ clrbits_le32(&gpio->dir, 0x00000400);
+ clrbits_le32(&gpio->out_data, 0x00000400);
+ /*
+ * PLC MDIO CLK
+ * GP6[9] = Out[14]
+ */
+ clrbits_le32(&gpio->dir, 0x00000200);
+ clrbits_le32(&gpio->out_data, 0x00000200);
+ /*
+ * HK218, active high
+ * GP6[8] = Out[15], set to 0
+ */
+ clrbits_le32(&gpio->dir, 0x00000100);
+ clrbits_le32(&gpio->out_data, 0x00000100);
+ /*
+ * SW reset TPM ctrl., active low
+ * GP6[0] = Out[13], set to 1
+ */
+ clrbits_le32(&gpio->dir, 0x00000001);
+ setbits_le32(&gpio->out_data, 0x00000001);
+
+ gpio = davinci_gpio_bank23;
+ /*
+ * LCM: Signal E
+ * GP2[2] = Out[8]
+ */
+ clrbits_le32(&gpio->dir, 0x00000004);
+ setbits_le32(&gpio->out_data, 0x00000004);
+
+ gpio = davinci_gpio_bank01;
+ /*
+ * PV-IF RS485 RxD Enable\
+ */
+ clrbits_le32(&gpio->dir, 0x00008000);
+ clrbits_le32(&gpio->out_data, 0x00008000);
+ /*
+ * set LED pins to output and state 0
+ */
+ clrbits_le32(&gpio->dir, 0x8000407e);
+ clrbits_le32(&gpio->out_data, 0x8000407e);
+
+ /*
+ * Set the LED 1 - 4 to on
+ */
+ cmc_set_led_state(&led_table[1], 1);
+ cmc_set_led_state(&led_table[2], 1);
+ cmc_set_led_state(&led_table[3], 1);
+ cmc_set_led_state(&led_table[4], 1);
+ return;
+}
@@ -128,6 +128,7 @@ davinci_dvevm arm arm926ejs dvevm davinci
davinci_schmoogie arm arm926ejs schmoogie davinci davinci
davinci_sffsdr arm arm926ejs sffsdr davinci davinci
davinci_sonata arm arm926ejs sonata davinci davinci
+enbw_cmc arm arm926ejs enbw_cmc enbw davinci
km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_DISABLE_PCI
km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood
mgcoge3un arm arm926ejs km_arm keymile kirkwood
new file mode 100644
@@ -0,0 +1,443 @@
+/*
+ * (C) Copyright 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Based on davinci_dvevm.h. Original Copyrights follow:
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Board
+ */
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_USE_NAND
+
+/*
+ * SoC Configuration
+ */
+#define CONFIG_ARM926EJS /* arm926ejs CPU core */
+#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
+#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
+#define CONFIG_SYS_OSCIN_FREQ 24000000
+#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
+#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_AM18018_LOWLEVEL
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_HOSTNAME enbw_cmc
+#define CONFIG_DISPLAY_CPUINFO
+
+#define MACH_TYPE_ENBW_CMC 3585
+#define CONFIG_MACH_TYPE MACH_TYPE_ENBW_CMC
+
+/*
+ * Memory Info
+ */
+#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
+#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
+#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
+#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
+
+/* memtest start addr */
+#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
+
+/* memtest will be run on 16MB */
+#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
+
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define CONFIG_STACKSIZE (256*1024) /* regular stack */
+
+/*
+ * Serial Driver info
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
+#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
+#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
+#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
+#define CONFIG_BAUDRATE 115200 /* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * I2C Configuration
+ */
+#define CONFIG_HARD_I2C
+#define CONFIG_DRIVER_DAVINCI_I2C
+#define CONFIG_SYS_I2C_SPEED 80000
+#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
+#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
+#define CONFIG_CMD_I2C
+
+#define CONFIG_CMD_DTT
+#define CONFIG_DTT_LM75
+#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
+#define CONFIG_SYS_DTT_MAX_TEMP 70
+#define CONFIG_SYS_DTT_LOW_TEMP -30
+#define CONFIG_SYS_DTT_HYSTERESIS 3
+
+/*
+ * Flash & Environment
+ */
+#ifdef CONFIG_USE_NAND
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+#define CONFIG_SYS_NAND_PAGE_2K
+#define CONFIG_SYS_NAND_CS 3
+#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
+#define CONFIG_SYS_CLE_MASK 0x10
+#define CONFIG_SYS_ALE_MASK 0x8
+#undef CONFIG_SYS_NAND_HW_ECC
+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
+#define NAND_MAX_CHIPS 1
+
+#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=davinci_nand.1"
+#define MTDPARTS_DEFAULT \
+ "mtdparts=" \
+ "physmap-flash.0:" \
+ "512k(U-Boot)," \
+ "64k(env1)," \
+ "64k(env2)," \
+ "-(rest);" \
+ "davinci_nand.1:" \
+ "128k(dtb)," \
+ "2m(kernel)," \
+ "4m(rootfs)," \
+ "-(userfs)"
+
+
+#define CONFIG_CMD_MTDPARTS
+
+#endif
+
+/*
+ * Network & Ethernet Configuration
+ */
+#ifdef CONFIG_DRIVER_TI_EMAC
+#define CONFIG_EMAC_MDIO_PHY_NUM 2
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT 10
+#define CONFIG_NET_MULTI
+#endif
+
+/*
+ * Flash configuration
+ */
+#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER 1
+#define CONFIG_SYS_FLASH_BASE 0x60000000
+#define CONFIG_SYS_FLASH_SIZE 0x01000000
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_MAX_FLASH_SECT 128
+#define CONFIG_FLASH_16BIT /* Flash is 16-bit */
+
+#define CONFIG_CMD_FLASH
+#define CONFIG_FLASH_SHOW_PROGRESS 99
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_SYS_MONITOR_LEN 0x80000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
+ CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE (64 << 10)
+#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \
+ CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+#undef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_DEFAULT_SETTINGS_ADDR (CONFIG_ENV_ADDR_REDUND + \
+ CONFIG_ENV_SECT_SIZE)
+
+#define xstr(s) str(s)
+#define str(s) #s
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "u-boot_addr_r=c0000000\0" \
+ "uboot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
+ "load=tftp ${u-boot_addr_r} ${uboot}\0" \
+ "update=protect off " xstr(CONFIG_SYS_FLASH_BASE) " +${filesize};"\
+ "erase " xstr(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
+ "cp.b ${u-boot_addr_r} " xstr(CONFIG_SYS_FLASH_BASE) \
+ " ${filesize};" \
+ "protect on " xstr(CONFIG_SYS_FLASH_BASE) " +${filesize}\0"\
+ "netdev=eth0\0" \
+ "rootpath=/opt/eldk-arm/arm\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "kernel_addr_r=c0700000\0" \
+ "fdt_addr_r=c0600000\0" \
+ "ramdisk_addr_r=c0a00000\0" \
+ "fdt_file=" xstr(CONFIG_HOSTNAME) "/" \
+ xstr(CONFIG_HOSTNAME) ".dtb\0" \
+ "kernel_file=" xstr(CONFIG_HOSTNAME) "/uImage \0" \
+ "nand_ld_ramdsk=nand read ${ramdisk_addr_r} 220000 400000;\0" \
+ "nand_ld_kernel=nand read ${kernel_addr_r} 20000 200000;\0" \
+ "nand_ld_fdt=nand read ${fdt_addr_r} 0 2000;\0" \
+ "load_kernel=tftp ${kernel_addr_r} ${kernel_file};\0" \
+ "load_fdt=tftp ${fdt_addr_r} ${fdt_file};\0" \
+ "load_nand=run nand_ld_ramdsk nand_ld_kernel nand_ld_fdt\0" \
+ "addcon=setenv bootargs ${bootargs} console=ttyS2," \
+ "${baudrate}n8\0" \
+ "net_nfs=run load_fdt load_kernel; " \
+ "run nfsargs addip addcon addmtd;" \
+ "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
+ "flash_self=run load_nand ramargs addip addcon;bootm " \
+ "${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \
+ "bootcmd=run net_nfs\0" \
+ "machid=e01\0" \
+ "key_cmd0=echo hallo0\0" \
+ "key_cmd1=echo hallo1\0" \
+ "key_cmd2=echo hallo2\0" \
+ "key_cmd3=echo hallo3\0" \
+ "key_magic_0=0\0" \
+ "key_magic_1=1\0" \
+ "key_magic_2=2\0" \
+ "key_magic_3=3\0" \
+ "magic_keys=0123\0" \
+ "hwconfig=switch:lan=on,pwl=off\0" \
+ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "mtdids=" MTDIDS_DEFAULT "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "logversion=2\0" \
+ "\0"
+
+/*
+ * U-Boot general configuration
+ */
+#define CONFIG_BOOTFILE "uImage" /* Boot file name */
+#define CONFIG_SYS_PROMPT "=> " /* Command Prompt */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
+#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_HWCONFIG
+
+/*
+ * U-Boot commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_CACHE
+
+#ifndef CONFIG_DRIVER_TI_EMAC
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_PING
+#endif
+
+#ifdef CONFIG_USE_NAND
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_NAND
+
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_LZO
+#define CONFIG_RBTREE
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#endif
+
+#if !defined(CONFIG_USE_NAND) && \
+ !defined(CONFIG_USE_NOR) && \
+ !defined(CONFIG_USE_SPIFLASH)
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_SIZE (16 << 10)
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_ENV
+#endif
+
+#define CONFIG_SYS_TEXT_BASE 0x60000000
+#define CONFIG_SYS_SDRAM_BASE 0xc0000000
+#define CONFIG_SYS_INIT_SP_ADDR (0x8001ff00)
+
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+ "echo"
+#define CONFIG_MISC_INIT_R 1
+
+#define CONFIG_CMC_RESET_PIN 0x04000000
+#define CONFIG_CMC_RESET_TIMEOUT 3
+
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_SYS_WDTTIMERBASE DAVINCI_TIMER1_BASE
+#define CONFIG_SYS_WDT_PERIOD_LOW 0x0c000000
+#define CONFIG_SYS_WDT_PERIOD_HIGH 0x0
+
+#define CONFIG_CMD_DATE
+#define CONFIG_RTC_DAVINCI
+
+/* FDT support */
+#define CONFIG_OF_LIBFDT 1
+
+/* LowLevel Init */
+/* PLL */
+#define CONFIG_SYS_DV_CLKMODE 0
+#define CONFIG_SYS_AM1808_PLL0_POSTDIV 1
+#define CONFIG_SYS_AM1808_PLL0_PLLDIV1 0x8000
+#define CONFIG_SYS_AM1808_PLL0_PLLDIV2 0x8001
+#define CONFIG_SYS_AM1808_PLL0_PLLDIV3 0x8002 /* 100MHz */
+#define CONFIG_SYS_AM1808_PLL0_PLLDIV4 0x8003
+#define CONFIG_SYS_AM1808_PLL0_PLLDIV5 0x8002
+#define CONFIG_SYS_AM1808_PLL0_PLLDIV6 CONFIG_SYS_AM1808_PLL0_PLLDIV1
+#define CONFIG_SYS_AM1808_PLL0_PLLDIV7 0x8005
+
+#define CONFIG_SYS_AM1808_PLL1_POSTDIV 1
+#define CONFIG_SYS_AM1808_PLL1_PLLDIV1 0x8000
+#define CONFIG_SYS_AM1808_PLL1_PLLDIV2 0x8001
+#define CONFIG_SYS_AM1808_PLL1_PLLDIV3 0x8002
+
+#define CONFIG_SYS_AM1808_PLL0_PLLM 37 /* PLL0 -> 456 MHz */
+#define CONFIG_SYS_AM1808_PLL1_PLLM 24 /* PLL1 -> 300 MHz */
+
+/* DDR RAM */
+#define CONFIG_SYS_AM1808_DDR2_DDRPHYCR (0 | \
+ (0x1 << 7) | \
+ (0x1 << 6) | \
+ (0x4 << 0))
+
+#define CONFIG_SYS_AM1808_DDR2_SDBCR (0 | \
+ (0 << DV_DDR_SDCR_DDR2TERM1_SHIFT) | \
+ (0 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \
+ (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
+ (0x1 << DV_DDR_SDCR_DDREN_SHIFT) | \
+ (0x1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
+ (0x1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT) | \
+ (0x1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
+ (0x3 << DV_DDR_SDCR_CL_SHIFT) | \
+ (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \
+ (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
+
+#define CONFIG_SYS_AM1808_DDR2_SDBCR2 4 /* 13 row address bits */
+
+/*
+ * freq = 132MHz -> t = 8ns
+ */
+#define CONFIG_SYS_AM1808_DDR2_SDTIMR (0 | \
+ (0x0c << 25) | /* tRFC = 105 105/8 = 13 - 1 = 0xc */ \
+ (1 << 22) | /* tRP 15/8 = 2 - 1 = 1 */ \
+ (1 << 19) | /* tRCD 15/8 = 2 - 1 = 1 */ \
+ (1 << 16) | /* tWR 15/8 = 2 - 1 = 1 */ \
+ (5 << 11) | /* tRAS 45/8 = 6 - 1 = 5 */ \
+ (7 << 6) | /* tRC 60/8 = 8 - 1 = 7 */ \
+ (1 << 3) | /* tRRD 12/8 = 2 -1 = 1 */ \
+ (readl(&dv_ddr2_regs_ctrl->sdtimr) & 0x4) | /* Reserved */ \
+ ((2 - 1) << 0)) /* tWTR 7.5 ns min 2 clocks */
+
+/*
+ * freq = 132MHz -> t=8ns
+ */
+#define CONFIG_SYS_AM1808_DDR2_SDTIMR2 (0 | \
+ (readl(&dv_ddr2_regs_ctrl->sdtimr2) & 0x80000000) | /* Reserved */ \
+ (8 << 27) | /* tRASMAX [(70us/7800ns)-1] */ \
+ (2 << 25) | /* tXP = 2, tCKe = 3 -> 3 - 1 = 2 */ \
+ (0 << 23) | /* tODT (Not supported) */ \
+ (13 << 16) | /* tXSNR = tRFC + 10 = 115 115/8 = 14 - 1 = 13 */ \
+ (24 << 8) | /* tXSRD = 200 200/8 = 25 - 1 = 24 */ \
+ (0 << 5) | /* tRTP = 7.5 7.5/8 = 1 - 1 = 0 */ \
+ (2 << 0)) /* tCKE = 3 -> 3 - 1 = 2 */
+
+#define CONFIG_SYS_AM1808_DDR2_SDRCR 0x00000407
+
+/*
+ * with Pin Setup Utility from TI
+ * missing GPIO pin setup
+ */
+#define CONFIG_SYS_AM1808_PINMUX0 0x44448888
+#define CONFIG_SYS_AM1808_PINMUX1 0x48888884
+#define CONFIG_SYS_AM1808_PINMUX2 0x88888888
+#define CONFIG_SYS_AM1808_PINMUX3 0x88888888
+#define CONFIG_SYS_AM1808_PINMUX4 0x22222288
+#define CONFIG_SYS_AM1808_PINMUX5 0x11111111
+#define CONFIG_SYS_AM1808_PINMUX6 0x11818811
+#define CONFIG_SYS_AM1808_PINMUX7 0x11111111
+#define CONFIG_SYS_AM1808_PINMUX8 0x11111111
+#define CONFIG_SYS_AM1808_PINMUX9 0x11111111
+#define CONFIG_SYS_AM1808_PINMUX10 0x11111111
+#define CONFIG_SYS_AM1808_PINMUX11 0x11111111
+#define CONFIG_SYS_AM1808_PINMUX12 0x11111111
+#define CONFIG_SYS_AM1808_PINMUX13 0x88888800
+#define CONFIG_SYS_AM1808_PINMUX14 0x00000088
+#define CONFIG_SYS_AM1808_PINMUX15 0x00000000
+#define CONFIG_SYS_AM1808_PINMUX16 0x88888880
+#define CONFIG_SYS_AM1808_PINMUX17 0x88888888
+#define CONFIG_SYS_AM1808_PINMUX18 0x88022288
+#define CONFIG_SYS_AM1808_PINMUX19 0x08022288
+
+#define CONFIG_SYS_AM1808_CS2CFG 0x08624311
+#define CONFIG_SYS_AM1808_CS3CFG 0x04222310
+
+/*
+ * NOR Bootconfiguration word:
+ * Method: Direc boot
+ * EMIFA access mode: 16 Bit
+ */
+#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
+
+#define CONFIG_POST (CONFIG_SYS_POST_MEMORY)
+#define CONFIG_SYS_POST_WORD_ADDR 0x8001FFF0
+#define CONFIG_LOGBUFFER
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_SYS_BOOTCOUNT_ADDR 0x01c23060
+
+#define CONFIG_SYS_NAND_U_BOOT_DST 0xc0080000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x60004000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x70000
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
+#define CONFIG_SYS_DCACHE_OFF
+#endif /* __CONFIG_H */
- booting from NOR Flash with direct boot method - POST support - LOGBUF support Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Paulraj Sandeep <s-paulraj@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Igor Grinberg <grinberg@compulab.co.il> --- - changes for v2 - use CONFIG_MACH_TYPE instead setting the MACH_TYPE in board specific code, as Igor Grinberg suggested. - add logversion=2 to default Environment board/enbw/enbw_cmc/Makefile | 51 ++++ board/enbw/enbw_cmc/enbw_cmc.c | 570 ++++++++++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/enbw_cmc.h | 443 +++++++++++++++++++++++++++++++ 4 files changed, 1065 insertions(+), 0 deletions(-) create mode 100644 board/enbw/enbw_cmc/Makefile create mode 100644 board/enbw/enbw_cmc/enbw_cmc.c create mode 100644 include/configs/enbw_cmc.h