From patchwork Sat Sep 17 16:13:00 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: nagabhushana.netagunte@ti.com X-Patchwork-Id: 115134 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 4F215B70BC for ; Sun, 18 Sep 2011 02:13:50 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 508202839E; Sat, 17 Sep 2011 18:13:40 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id S44qEtgmNMHT; Sat, 17 Sep 2011 18:13:40 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8579D283A2; Sat, 17 Sep 2011 18:13:21 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1AA0B282F4 for ; Sat, 17 Sep 2011 18:13:18 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id kNQAn+nKQK0Y for ; Sat, 17 Sep 2011 18:13:16 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from arroyo.ext.ti.com (arroyo.ext.ti.com [192.94.94.40]) by theia.denx.de (Postfix) with ESMTPS id 31E53282D7 for ; Sat, 17 Sep 2011 18:13:12 +0200 (CEST) Received: from dbdp20.itg.ti.com ([172.24.170.38]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id p8HGD79V017436 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Sat, 17 Sep 2011 11:13:10 -0500 Received: from dbde71.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id p8HGD64j004834 for ; Sat, 17 Sep 2011 21:43:07 +0530 (IST) Received: from dbdp31.itg.ti.com (172.24.170.98) by DBDE71.ent.ti.com (172.24.170.149) with Microsoft SMTP Server id 8.3.106.1; Sat, 17 Sep 2011 21:43:06 +0530 Received: from psplinux051.india.ti.com (psplinux051.india.ti.com [172.24.162.244]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id p8HGD5Il004161; Sat, 17 Sep 2011 21:43:06 +0530 (IST) Received: from psplinux051.india.ti.com (localhost [127.0.0.1]) by psplinux051.india.ti.com (8.13.1/8.13.1) with ESMTP id p8HGD5PI011645; Sat, 17 Sep 2011 21:43:05 +0530 Received: (from x0144960@localhost) by psplinux051.india.ti.com (8.13.1/8.13.1/Submit) id p8HGD5Zl011642; Sat, 17 Sep 2011 21:43:05 +0530 From: To: Date: Sat, 17 Sep 2011 21:43:00 +0530 Message-ID: <1316275984-11586-2-git-send-email-nagabhushana.netagunte@ti.com> X-Mailer: git-send-email 1.6.2.4 In-Reply-To: <1316275984-11586-1-git-send-email-nagabhushana.netagunte@ti.com> References: <1316275984-11586-1-git-send-email-nagabhushana.netagunte@ti.com> MIME-Version: 1.0 Cc: sudhakar.raj@ti.com, manjunath.hadli@ti.com Subject: [U-Boot] [PATCH 1/5] davinci : move clock related functions to new file X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Nagabhushana Netagunte move the functions related to clock from cpu.c to the new file speed.c. Signed-off-by: Nagabhushana Netagunte --- arch/arm/cpu/arm926ejs/davinci/Makefile | 2 +- arch/arm/cpu/arm926ejs/davinci/cpu.c | 173 --------------------------- arch/arm/cpu/arm926ejs/davinci/speed.c | 196 +++++++++++++++++++++++++++++++ 3 files changed, 197 insertions(+), 174 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/davinci/speed.c diff --git a/arch/arm/cpu/arm926ejs/davinci/Makefile b/arch/arm/cpu/arm926ejs/davinci/Makefile index 3183e6a..5630228 100644 --- a/arch/arm/cpu/arm926ejs/davinci/Makefile +++ b/arch/arm/cpu/arm926ejs/davinci/Makefile @@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o -COBJS-y += cpu.o timer.o psc.o +COBJS-y += cpu.o timer.o psc.o speed.o COBJS-$(CONFIG_SOC_DM355) += dm355.o COBJS-$(CONFIG_SOC_DM365) += dm365.o COBJS-$(CONFIG_SOC_DM644X) += dm644x.o diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c b/arch/arm/cpu/arm926ejs/davinci/cpu.c index b705dfd..c2f72d6 100644 --- a/arch/arm/cpu/arm926ejs/davinci/cpu.c +++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c @@ -22,179 +22,6 @@ #include #include -#include -#include - -/* offsets from PLL controller base */ -#define PLLC_PLLCTL 0x100 -#define PLLC_PLLM 0x110 -#define PLLC_PREDIV 0x114 -#define PLLC_PLLDIV1 0x118 -#define PLLC_PLLDIV2 0x11c -#define PLLC_PLLDIV3 0x120 -#define PLLC_POSTDIV 0x128 -#define PLLC_BPDIV 0x12c -#define PLLC_PLLDIV4 0x160 -#define PLLC_PLLDIV5 0x164 -#define PLLC_PLLDIV6 0x168 -#define PLLC_PLLDIV7 0x16c -#define PLLC_PLLDIV8 0x170 -#define PLLC_PLLDIV9 0x174 - -#define BIT(x) (1 << (x)) - -/* SOC-specific pll info */ -#ifdef CONFIG_SOC_DM355 -#define ARM_PLLDIV PLLC_PLLDIV1 -#define DDR_PLLDIV PLLC_PLLDIV1 -#endif - -#ifdef CONFIG_SOC_DM644X -#define ARM_PLLDIV PLLC_PLLDIV2 -#define DSP_PLLDIV PLLC_PLLDIV1 -#define DDR_PLLDIV PLLC_PLLDIV2 -#endif - -#ifdef CONFIG_SOC_DM646X -#define DSP_PLLDIV PLLC_PLLDIV1 -#define ARM_PLLDIV PLLC_PLLDIV2 -#define DDR_PLLDIV PLLC_PLLDIV1 -#endif - -#ifdef CONFIG_SOC_DA8XX -unsigned int sysdiv[9] = { - PLLC_PLLDIV1, PLLC_PLLDIV2, PLLC_PLLDIV3, PLLC_PLLDIV4, PLLC_PLLDIV5, - PLLC_PLLDIV6, PLLC_PLLDIV7, PLLC_PLLDIV8, PLLC_PLLDIV9 -}; - -int clk_get(enum davinci_clk_ids id) -{ - int pre_div; - int pllm; - int post_div; - int pll_out; - unsigned int pll_base; - - pll_out = CONFIG_SYS_OSCIN_FREQ; - - if (id == DAVINCI_AUXCLK_CLKID) - goto out; - - if ((id >> 16) == 1) - pll_base = (unsigned int)davinci_pllc1_regs; - else - pll_base = (unsigned int)davinci_pllc0_regs; - - id &= 0xFFFF; - - /* - * Lets keep this simple. Combining operations can result in - * unexpected approximations - */ - pre_div = (readl(pll_base + PLLC_PREDIV) & - DAVINCI_PLLC_DIV_MASK) + 1; - pllm = readl(pll_base + PLLC_PLLM) + 1; - - pll_out /= pre_div; - pll_out *= pllm; - - if (id == DAVINCI_PLLM_CLKID) - goto out; - - post_div = (readl(pll_base + PLLC_POSTDIV) & - DAVINCI_PLLC_DIV_MASK) + 1; - - pll_out /= post_div; - - if (id == DAVINCI_PLLC_CLKID) - goto out; - - pll_out /= (readl(pll_base + sysdiv[id - 1]) & - DAVINCI_PLLC_DIV_MASK) + 1; - -out: - return pll_out; -} -#endif /* CONFIG_SOC_DA8XX */ - -#ifdef CONFIG_DISPLAY_CPUINFO - -static unsigned pll_div(volatile void *pllbase, unsigned offset) -{ - u32 div; - - div = REG(pllbase + offset); - return (div & BIT(15)) ? (1 + (div & 0x1f)) : 1; -} - -static inline unsigned pll_prediv(volatile void *pllbase) -{ -#ifdef CONFIG_SOC_DM355 - /* this register read seems to fail on pll0 */ - if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE) - return 8; - else - return pll_div(pllbase, PLLC_PREDIV); -#endif - return 1; -} - -static inline unsigned pll_postdiv(volatile void *pllbase) -{ -#ifdef CONFIG_SOC_DM355 - return pll_div(pllbase, PLLC_POSTDIV); -#elif defined(CONFIG_SOC_DM6446) - if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE) - return pll_div(pllbase, PLLC_POSTDIV); -#endif - return 1; -} - -static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div) -{ - volatile void *pllbase = (volatile void *) pll_addr; -#ifdef CONFIG_SOC_DM646X - unsigned base = CFG_REFCLK_FREQ / 1000; -#else - unsigned base = CONFIG_SYS_HZ_CLOCK / 1000; -#endif - - /* the PLL might be bypassed */ - if (REG(pllbase + PLLC_PLLCTL) & BIT(0)) { - base /= pll_prediv(pllbase); - base *= 1 + (REG(pllbase + PLLC_PLLM) & 0x0ff); - base /= pll_postdiv(pllbase); - } - return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div)); -} - -int print_cpuinfo(void) -{ - /* REVISIT fetch and display CPU ID and revision information - * too ... that will matter as more revisions appear. - */ - printf("Cores: ARM %d MHz", - pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV)); - -#ifdef DSP_PLLDIV - printf(", DSP %d MHz", - pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV)); -#endif - - printf("\nDDR: %d MHz\n", - /* DDR PHY uses an x2 input clock */ - pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, DDR_PLLDIV) - / 2); - return 0; -} - -#ifdef DAVINCI_DM6467EVM -unsigned int davinci_arm_clk_get() -{ - return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV) * 1000000; -} -#endif -#endif /* * Initializes on-chip ethernet controllers. diff --git a/arch/arm/cpu/arm926ejs/davinci/speed.c b/arch/arm/cpu/arm926ejs/davinci/speed.c new file mode 100644 index 0000000..9dace9e --- /dev/null +++ b/arch/arm/cpu/arm926ejs/davinci/speed.c @@ -0,0 +1,196 @@ +/* + * (C) Copyright 2011 + * Texas Instruments, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* offsets from PLL controller base */ +#define PLLC_PLLCTL 0x100 +#define PLLC_PLLM 0x110 +#define PLLC_PREDIV 0x114 +#define PLLC_PLLDIV1 0x118 +#define PLLC_PLLDIV2 0x11c +#define PLLC_PLLDIV3 0x120 +#define PLLC_POSTDIV 0x128 +#define PLLC_BPDIV 0x12c +#define PLLC_PLLDIV4 0x160 +#define PLLC_PLLDIV5 0x164 +#define PLLC_PLLDIV6 0x168 +#define PLLC_PLLDIV7 0x16c +#define PLLC_PLLDIV8 0x170 +#define PLLC_PLLDIV9 0x174 + +#define BIT(x) (1 << (x)) + +/* SOC-specific pll info */ +#ifdef CONFIG_SOC_DM355 +#define ARM_PLLDIV PLLC_PLLDIV1 +#define DDR_PLLDIV PLLC_PLLDIV1 +#endif + +#ifdef CONFIG_SOC_DM644X +#define ARM_PLLDIV PLLC_PLLDIV2 +#define DSP_PLLDIV PLLC_PLLDIV1 +#define DDR_PLLDIV PLLC_PLLDIV2 +#endif + +#ifdef CONFIG_SOC_DM646X +#define DSP_PLLDIV PLLC_PLLDIV1 +#define ARM_PLLDIV PLLC_PLLDIV2 +#define DDR_PLLDIV PLLC_PLLDIV1 +#endif + +#ifdef CONFIG_SOC_DA8XX +unsigned int sysdiv[9] = { + PLLC_PLLDIV1, PLLC_PLLDIV2, PLLC_PLLDIV3, PLLC_PLLDIV4, PLLC_PLLDIV5, + PLLC_PLLDIV6, PLLC_PLLDIV7, PLLC_PLLDIV8, PLLC_PLLDIV9 +}; + +int clk_get(enum davinci_clk_ids id) +{ + int pre_div; + int pllm; + int post_div; + int pll_out; + unsigned int pll_base; + + pll_out = CONFIG_SYS_OSCIN_FREQ; + + if (id == DAVINCI_AUXCLK_CLKID) + goto out; + + if ((id >> 16) == 1) + pll_base = (unsigned int)davinci_pllc1_regs; + else + pll_base = (unsigned int)davinci_pllc0_regs; + + id &= 0xFFFF; + + /* + * Lets keep this simple. Combining operations can result in + * unexpected approximations + */ + pre_div = (readl(pll_base + PLLC_PREDIV) & + DAVINCI_PLLC_DIV_MASK) + 1; + pllm = readl(pll_base + PLLC_PLLM) + 1; + + pll_out /= pre_div; + pll_out *= pllm; + + if (id == DAVINCI_PLLM_CLKID) + goto out; + + post_div = (readl(pll_base + PLLC_POSTDIV) & + DAVINCI_PLLC_DIV_MASK) + 1; + + pll_out /= post_div; + + if (id == DAVINCI_PLLC_CLKID) + goto out; + + pll_out /= (readl(pll_base + sysdiv[id - 1]) & + DAVINCI_PLLC_DIV_MASK) + 1; + +out: + return pll_out; +} +#endif /* CONFIG_SOC_DA8XX */ + +#ifdef CONFIG_DISPLAY_CPUINFO + +static unsigned pll_div(volatile void *pllbase, unsigned offset) +{ + u32 div; + + div = REG(pllbase + offset); + return (div & BIT(15)) ? (1 + (div & 0x1f)) : 1; +} + +static inline unsigned pll_prediv(volatile void *pllbase) +{ +#ifdef CONFIG_SOC_DM355 + /* this register read seems to fail on pll0 */ + if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE) + return 8; + else + return pll_div(pllbase, PLLC_PREDIV); +#endif + return 1; +} + +static inline unsigned pll_postdiv(volatile void *pllbase) +{ +#ifdef CONFIG_SOC_DM355 + return pll_div(pllbase, PLLC_POSTDIV); +#elif defined(CONFIG_SOC_DM6446) + if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE) + return pll_div(pllbase, PLLC_POSTDIV); +#endif + return 1; +} + +static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div) +{ + volatile void *pllbase = (volatile void *) pll_addr; +#ifdef CONFIG_SOC_DM646X + unsigned base = CFG_REFCLK_FREQ / 1000; +#else + unsigned base = CONFIG_SYS_HZ_CLOCK / 1000; +#endif + + /* the PLL might be bypassed */ + if (REG(pllbase + PLLC_PLLCTL) & BIT(0)) { + base /= pll_prediv(pllbase); + base *= 1 + (REG(pllbase + PLLC_PLLM) & 0x0ff); + base /= pll_postdiv(pllbase); + } + return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div)); +} + +int print_cpuinfo(void) +{ + /* REVISIT fetch and display CPU ID and revision information + * too ... that will matter as more revisions appear. + */ + printf("Cores: ARM %d MHz", + pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV)); + +#ifdef DSP_PLLDIV + printf(", DSP %d MHz", + pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV)); +#endif + + printf("\nDDR: %d MHz\n", + /* DDR PHY uses an x2 input clock */ + pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, DDR_PLLDIV) + / 2); + return 0; +} + +#ifdef DAVINCI_DM6467EVM +unsigned int davinci_arm_clk_get() +{ + return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV) * 1000000; +} +#endif +#endif