From patchwork Wed Aug 10 11:34:59 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajay Bhargav X-Patchwork-Id: 109369 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id CAC47B6F87 for ; Wed, 10 Aug 2011 21:35:34 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 30D27283A8; Wed, 10 Aug 2011 13:35:26 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id BU7X6wXqKDIZ; Wed, 10 Aug 2011 13:35:25 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5002A28398; Wed, 10 Aug 2011 13:35:18 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id AC7952835B for ; Wed, 10 Aug 2011 13:35:12 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id gOlm4UxVQ+Zl for ; Wed, 10 Aug 2011 13:35:06 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from ahm.einfochips.com (unknown [203.76.128.206]) by theia.denx.de (Postfix) with ESMTP id 77EA62830B for ; Wed, 10 Aug 2011 13:35:02 +0200 (CEST) Received: from localhost (localhost.localdomain [127.0.0.1]) by ahm.einfochips.com (Postfix) with ESMTP id 85B18A608018; Wed, 10 Aug 2011 16:54:51 +0530 (IST) X-Virus-Scanned: amavisd-new at einfochips.com Received: from ahm.einfochips.com ([127.0.0.1]) by localhost (ahm.einfochips.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id mpW+Q26d9Wy4; Wed, 10 Aug 2011 16:54:51 +0530 (IST) Received: from localhost.localdomain (unknown [192.168.9.91]) by ahm.einfochips.com (Postfix) with ESMTPA id 6F6A4A608004; Wed, 10 Aug 2011 16:54:51 +0530 (IST) From: Ajay Bhargav To: prafulla@marvell.com Date: Wed, 10 Aug 2011 17:04:59 +0530 Message-Id: <1312976100-27345-1-git-send-email-ajay.bhargav@einfochips.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: References: Cc: u-boot@lists.denx.de, Ajay Bhargav Subject: [U-Boot] [PATCH v5 1/2] gpio: Add GPIO driver framework for Marvell SoCs X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This patch adds generic GPIO driver framework support for Marvell SoCs. To enable GPIO driver define CONFIG_MARVELL_GPIO and for GPIO commands define CONFIG_CMD_GPIO in your board configuration file. Signed-off-by: Ajay Bhargav Acked-by: Prafulla Wadaskar --- Changes for v2: - mvgpio.h removed - function get_gpio_base moved to gpio.h - error messages added Changes for v3: - Added mvgpio.h for common define based on CPU core subversion. Changes for v4: - not changed Changes for v5: - Added change history drivers/gpio/Makefile | 1 + drivers/gpio/mvgpio.c | 114 +++++++++++++++++++++++++++++++++++++++++++++++++ include/mvgpio.h | 77 +++++++++++++++++++++++++++++++++ 3 files changed, 192 insertions(+), 0 deletions(-) create mode 100644 drivers/gpio/mvgpio.c create mode 100644 include/mvgpio.h diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 62ec97d..beca1da 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -27,6 +27,7 @@ LIB := $(obj)libgpio.o COBJS-$(CONFIG_AT91_GPIO) += at91_gpio.o COBJS-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o +COBJS-$(CONFIG_MARVELL_GPIO) += mvgpio.o COBJS-$(CONFIG_MARVELL_MFP) += mvmfp.o COBJS-$(CONFIG_MXC_GPIO) += mxc_gpio.o COBJS-$(CONFIG_PCA953X) += pca953x.o diff --git a/drivers/gpio/mvgpio.c b/drivers/gpio/mvgpio.c new file mode 100644 index 0000000..0cc8ed7 --- /dev/null +++ b/drivers/gpio/mvgpio.c @@ -0,0 +1,114 @@ +/* + * (C) Copyright 2011 + * eInfochips Ltd. + * Written-by: Ajay Bhargav + * + * (C) Copyright 2010 + * Marvell Semiconductor + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include +#include +#include +#include + +#ifndef MV_MAX_GPIO +#define MV_MAX_GPIO 128 +#endif + +int gpio_request(int gp, const char *label) +{ + if (gp >= MV_MAX_GPIO) { + printf("%s: Invalid GPIO requested %d\n", __func__, gp); + return -EINVAL; + } + return 0; +} + +void gpio_free(int gp) +{ +} + +void gpio_toggle_value(int gp) +{ + gpio_set_value(gp, !gpio_get_value(gp)); +} + +int gpio_direction_input(int gp) +{ + struct gpio_reg *gpio_reg_bank; + + if (gp >= MV_MAX_GPIO) { + printf("%s: Invalid GPIO %d\n", __func__, gp); + return -EINVAL; + } + + gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp)); + writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gcdr); + return 0; +} + +int gpio_direction_output(int gp, int value) +{ + struct gpio_reg *gpio_reg_bank; + + if (gp >= MV_MAX_GPIO) { + printf("%s: Invalid GPIO %d\n", __func__, gp); + return -EINVAL; + } + + gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp)); + writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gsdr); + gpio_set_value(gp, value); + return 0; +} + +int gpio_get_value(int gp) +{ + struct gpio_reg *gpio_reg_bank; + u32 gp_val; + + if (gp >= MV_MAX_GPIO) { + printf("%s: Invalid GPIO %d\n", __func__, gp); + return -EINVAL; + } + + gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp)); + gp_val = readl(&gpio_reg_bank->gplr); + + return GPIO_VAL(gp, gp_val); +} + +void gpio_set_value(int gp, int value) +{ + struct gpio_reg *gpio_reg_bank; + + if (gp >= MV_MAX_GPIO) { + printf("%s: Invalid GPIO %d\n", __func__, gp); + return; + } + + gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp)); + if (value) + writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gpsr); + else + writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gpcr); +} diff --git a/include/mvgpio.h b/include/mvgpio.h new file mode 100644 index 0000000..768e94c --- /dev/null +++ b/include/mvgpio.h @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2011 + * eInfochips Ltd. + * Written-by: Ajay Bhargav + * + * (C) Copyright 2010 + * Marvell Semiconductor + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __MVGPIO_H__ +#define __MVGPIO_H__ + +#include + +#define GPIO_SET 1 +#define GPIO_CLR 0 + +#ifdef CONFIG_SHEEVA_88SV331xV5 +/* + * GPIO Register map for SHEEVA 88SV331xV5 + */ +struct gpio_reg { + u32 gplr; /* Pin Level Register - 0x0000 */ + u32 pad0[2]; + u32 gpdr; /* Pin Direction Register - 0x000C */ + u32 pad1[2]; + u32 gpsr; /* Pin Output Set Register - 0x0018 */ + u32 pad2[2]; + u32 gpcr; /* Pin Output Clear Register - 0x0024 */ + u32 pad3[2]; + u32 grer; /* Rising-Edge Detect Enable Register - 0x0030 */ + u32 pad4[2]; + u32 gfer; /* Falling-Edge Detect Enable Register - 0x003C */ + u32 pad5[2]; + u32 gedr; /* Edge Detect Status Register - 0x0048 */ + u32 pad6[2]; + u32 gsdr; /* Bitwise Set of GPIO Direction Register - 0x0054 */ + u32 pad7[2]; + u32 gcdr; /* Bitwise Clear of GPIO Direction Register - 0x0060 */ + u32 pad8[2]; + u32 gsrer; /* Bitwise Set of Rising-Edge Detect Enable + Register - 0x006C */ + u32 pad9[2]; + u32 gcrer; /* Bitwise Clear of Rising-Edge Detect Enable + Register - 0x0078 */ + u32 pad10[2]; + u32 gsfer; /* Bitwise Set of Falling-Edge Detect Enable + Register - 0x0084 */ + u32 pad11[2]; + u32 gcfer; /* Bitwise Clear of Falling-Edge Detect Enable + Register - 0x0090 */ + u32 pad12[2]; + u32 apmask; /* Bitwise Mask of Edge Detect Register - 0x009C */ +}; +#else +#error "CPU core subversion not defined" +#endif + +#endif /* __MVGPIO_H__ */