@@ -380,8 +380,14 @@ struct davinci_pllc_regs {
#define DAVINCI_PLLC_DIV_MASK 0x1f
#define ASYNC3 get_async3_src()
+#define EMIFB get_emifb_src()
+
+#define PLL1_PLLM ((1 << 16) | DAVINCI_PLLM_CLKID)
+#define PLL1_SYSCLK1 ((1 << 16) | 0x1)
#define PLL1_SYSCLK2 ((1 << 16) | 0x2)
#define DAVINCI_SPI1_CLKID (cpu_is_da830() ? 2 : ASYNC3)
+#define DAVINCI_DDR_CLKID EMIFB
+
/* Clock IDs */
enum davinci_clk_ids {
DAVINCI_SPI0_CLKID = 2,
@@ -485,6 +491,12 @@ static inline int get_async3_src(void)
PLL1_SYSCLK2 : 2;
}
+static inline int get_emifb_src(void)
+{
+ return (REG(&davinci_syscfg_regs->cfgchip3) & 0x80) ?
+ PLL1_PLLM : PLL1_SYSCLK1;
+}
+
#endif /* CONFIG_SOC_DA8XX */
#endif /* __ASM_ARCH_HARDWARE_H */
@@ -502,6 +502,7 @@ int misc_init_r(void)
int ret;
printf("ARM Clock : %d Hz\n", clk_get(DAVINCI_ARM_CLKID));
+ printf("DDR Clock : %d Hz\n", clk_get(DAVINCI_DDR_CLKID)/2);
if (getenv("ethaddr") == NULL) {
/* Read Ethernet MAC address from EEPROM */