From patchwork Wed Jul 27 11:22:38 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Schwierzeck X-Patchwork-Id: 107037 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id D1F73B6F00 for ; Wed, 27 Jul 2011 21:23:49 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9FD7F280B2; Wed, 27 Jul 2011 13:23:46 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id J+QQwfPZs9JS; Wed, 27 Jul 2011 13:23:46 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8E888280B5; Wed, 27 Jul 2011 13:23:05 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2EEBF2809B for ; Wed, 27 Jul 2011 13:22:57 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ql3TbnV5g4pz for ; Wed, 27 Jul 2011 13:22:53 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-fx0-f50.google.com (mail-fx0-f50.google.com [209.85.161.50]) by theia.denx.de (Postfix) with ESMTPS id 0A0B828094 for ; Wed, 27 Jul 2011 13:22:50 +0200 (CEST) Received: by mail-fx0-f50.google.com with SMTP id 2so195306fxh.23 for ; Wed, 27 Jul 2011 04:22:50 -0700 (PDT) Received: by 10.223.10.143 with SMTP id p15mr8044235fap.12.1311765770896; Wed, 27 Jul 2011 04:22:50 -0700 (PDT) Received: from localhost.localdomain (dslb-088-073-238-191.pools.arcor-ip.net [88.73.238.191]) by mx.google.com with ESMTPS id p17sm12652fak.1.2011.07.27.04.22.49 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 27 Jul 2011 04:22:50 -0700 (PDT) From: Daniel Schwierzeck To: u-boot@lists.denx.de Date: Wed, 27 Jul 2011 13:22:38 +0200 Message-Id: <1311765759-18190-4-git-send-email-daniel.schwierzeck@googlemail.com> X-Mailer: git-send-email 1.7.6 In-Reply-To: <1311765759-18190-1-git-send-email-daniel.schwierzeck@googlemail.com> References: <1311765759-18190-1-git-send-email-daniel.schwierzeck@googlemail.com> Cc: Shinya Kuribayashi Subject: [U-Boot] [PATCH 3/4] MIPS: make cache operation mode configurable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Currently the cache operation mode is hard-coded to CONF_CM_CACHABLE_NONCOHERENT. This is not appropiate for CPUs or SOCs which operate at a different mode. This patch makes the cache operation mode configurable via board config. Signed-off-by: Daniel Schwierzeck --- arch/mips/cpu/mips32/start.S | 6 +++++- 1 files changed, 5 insertions(+), 1 deletions(-) diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S index e829b02..9c1b2f7 100644 --- a/arch/mips/cpu/mips32/start.S +++ b/arch/mips/cpu/mips32/start.S @@ -27,6 +27,10 @@ #include #include +#ifndef CONFIG_SYS_MIPS_CACHE_MODE +#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT +#endif + /* * For the moment disable interrupts, mark the kernel mode and * set ST0_KX so that the CPU does not spit fire when using @@ -249,7 +253,7 @@ reset: nop /* ... and enable them */ - li t0, CONF_CM_CACHABLE_NONCOHERENT + li t0, CONFIG_SYS_MIPS_CACHE_MODE mtc0 t0, CP0_CONFIG #endif