diff mbox

[U-Boot,v3,6/7] Timer: Fix at91rm9200/spi.c timer usage

Message ID 1310809041-3442-1-git-send-email-graeme.russ@gmail.com
State Accepted
Delegated to: Wolfgang Denk
Headers show

Commit Message

Graeme Russ July 16, 2011, 9:37 a.m. UTC
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
---
Changes since v2:
 - Added Signed-off-by

Changes since v1 ((WIP) [Timer]API Rewrite):
 - Rebased to 68d4230c3ccce96a72c5b99e48399bf1796fe3c6

 arch/arm/cpu/arm920t/at91rm9200/spi.c |    5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)

--
1.7.5.2.317.g391b14

Comments

Wolfgang Denk July 26, 2011, 12:54 p.m. UTC | #1
Dear Graeme Russ,

In message <1310809041-3442-1-git-send-email-graeme.russ@gmail.com> you wrote:
> Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
> ---
> Changes since v2:
>  - Added Signed-off-by
> 
> Changes since v1 ((WIP) [Timer]API Rewrite):
>  - Rebased to 68d4230c3ccce96a72c5b99e48399bf1796fe3c6
> 
>  arch/arm/cpu/arm920t/at91rm9200/spi.c |    5 +++--
>  1 files changed, 3 insertions(+), 2 deletions(-)

Applied, thanks.

Best regards,

Wolfgang Denk
diff mbox

Patch

diff --git a/arch/arm/cpu/arm920t/at91rm9200/spi.c b/arch/arm/cpu/arm920t/at91rm9200/spi.c
index f3cb5d8..c70efc6 100644
--- a/arch/arm/cpu/arm920t/at91rm9200/spi.c
+++ b/arch/arm/cpu/arm920t/at91rm9200/spi.c
@@ -108,6 +108,7 @@  void AT91F_SpiEnable(int cs)
 unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc )
 {
 	unsigned int timeout;
+	unsigned long start;

 	pDesc->state = BUSY;

@@ -132,12 +133,12 @@  unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc )
 	}

 	/* arm simple, non interrupt dependent timer */
-	reset_timer_masked();
+	start = get_timer(0);
 	timeout = 0;

 	AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN;
 	while(!(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RXBUFF) &&
-		((timeout = get_timer_masked() ) < CONFIG_SYS_SPI_WRITE_TOUT));
+		((timeout = get_timer(start) ) < CONFIG_SYS_SPI_WRITE_TOUT));
 	AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
 	pDesc->state = IDLE;