From patchwork Tue Jun 7 06:35:05 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Eric Benard X-Patchwork-Id: 99088 X-Patchwork-Delegate: info@emk-elektronik.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 8BFE5B6FA5 for ; Tue, 7 Jun 2011 16:51:10 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C135A281AB; Tue, 7 Jun 2011 08:51:08 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id xgkYx5I6+MA3; Tue, 7 Jun 2011 08:51:08 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2DD5B281AD; Tue, 7 Jun 2011 08:51:06 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BBBBA281AD for ; Tue, 7 Jun 2011 08:51:03 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id C5oQlIMdBa1D for ; Tue, 7 Jun 2011 08:51:02 +0200 (CEST) X-Greylist: delayed 600 seconds by postgrey-1.27 at theia; Tue, 07 Jun 2011 08:51:01 CEST X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from 97.mail-out.ovh.net (28.97.mail-out.ovh.net [87.98.186.139]) by theia.denx.de (Postfix) with ESMTP id 5A871281AB for ; Tue, 7 Jun 2011 08:51:01 +0200 (CEST) Received: from mail183.ha.ovh.net (b6.ovh.net [213.186.33.56]) by 97.mail-out.ovh.net (Postfix) with SMTP id 149FF4A61C6 for ; Tue, 7 Jun 2011 08:35:37 +0200 (CEST) Received: from b0.ovh.net (HELO queueout) (213.186.33.50) by b0.ovh.net with SMTP; 7 Jun 2011 08:35:13 +0200 Received: from tal33-3-82-233-81-124.fbx.proxad.net (HELO localhost.localdomain) (ebenard%eukrea.com@82.233.81.124) by ns0.ovh.net with SMTP; 7 Jun 2011 08:35:11 +0200 From: =?UTF-8?q?Eric=20B=C3=A9nard?= To: u-boot@lists.denx.de Date: Tue, 7 Jun 2011 08:35:05 +0200 Message-Id: <1307428508-26058-2-git-send-email-eric@eukrea.com> X-Mailer: git-send-email 1.7.4.4 In-Reply-To: <1307428508-26058-1-git-send-email-eric@eukrea.com> References: <1307428508-26058-1-git-send-email-eric@eukrea.com> MIME-Version: 1.0 X-Ovh-Tracer-Id: 14312158142363774235 X-Ovh-Remote: 82.233.81.124 (tal33-3-82-233-81-124.fbx.proxad.net) X-Ovh-Local: 213.186.33.20 (ns0.ovh.net) X-Spam-Check: DONE|U 0.5/N X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: 0 X-VR-SPAMCAUSE: Vade Retro 01.320.21 AV+AS Profile: OVH; Bailout: 300; Subject: [U-Boot] [PATCH 2/5] include/asm/arch-at91: update several .h files to ATMEL_xxx name scheme X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Signed-off-by: Eric Bénard --- arch/arm/include/asm/arch-at91/at91_matrix.h | 10 +++--- arch/arm/include/asm/arch-at91/at91_rstc.h | 2 +- arch/arm/include/asm/arch-at91/at91_wdt.h | 2 +- arch/arm/include/asm/arch-at91/at91sam9_sdramc.h | 30 +++++++++++----------- arch/arm/include/asm/arch-at91/at91sam9_smc.h | 12 ++++---- 5 files changed, 28 insertions(+), 28 deletions(-) diff --git a/arch/arm/include/asm/arch-at91/at91_matrix.h b/arch/arm/include/asm/arch-at91/at91_matrix.h index f99b1d4..a9ba9e9 100644 --- a/arch/arm/include/asm/arch-at91/at91_matrix.h +++ b/arch/arm/include/asm/arch-at91/at91_matrix.h @@ -26,18 +26,18 @@ #ifdef __ASSEMBLY__ #if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) -#define AT91_ASM_MATRIX_CSA0 (AT91_MATRIX_BASE + 0x11C) +#define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x11C) #elif defined(CONFIG_AT91SAM9261) -#define AT91_ASM_MATRIX_CSA0 (AT91_MATRIX_BASE + 0x30) +#define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x30) #elif defined(CONFIG_AT91SAM9263) -#define AT91_ASM_MATRIX_CSA0 (AT91_MATRIX_BASE + 0x120) +#define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x120) #elif defined(CONFIG_AT91SAM9G45) -#define AT91_ASM_MATRIX_CSA0 (AT91_MATRIX_BASE + 0x128) +#define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x128) #else #error AT91_ASM_MATRIX_CSA0 is not definied for current CPU #endif -#define AT91_ASM_MATRIX_MCFG AT91_MATRIX_BASE +#define AT91_ASM_MATRIX_MCFG ATMEL_BASE_MATRIX #else #if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) diff --git a/arch/arm/include/asm/arch-at91/at91_rstc.h b/arch/arm/include/asm/arch-at91/at91_rstc.h index 510eed5..15ffd18 100644 --- a/arch/arm/include/asm/arch-at91/at91_rstc.h +++ b/arch/arm/include/asm/arch-at91/at91_rstc.h @@ -16,7 +16,7 @@ #ifndef AT91_RSTC_H #define AT91_RSTC_H -#define AT91_ASM_RSTC_MR (AT91_RSTC_BASE + 0x08) +#define AT91_ASM_RSTC_MR (ATMEL_BASE_RSTC + 0x08) #ifndef __ASSEMBLY__ diff --git a/arch/arm/include/asm/arch-at91/at91_wdt.h b/arch/arm/include/asm/arch-at91/at91_wdt.h index cf08daf..dc22ea1 100644 --- a/arch/arm/include/asm/arch-at91/at91_wdt.h +++ b/arch/arm/include/asm/arch-at91/at91_wdt.h @@ -19,7 +19,7 @@ #ifdef __ASSEMBLY__ -#define AT91_ASM_WDT_MR (AT91_WDT_BASE + 0x04) +#define AT91_ASM_WDT_MR (ATMEL_BASE_WDT + 0x04) #else diff --git a/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h b/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h index c3da3a6..54159a7 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h +++ b/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h @@ -19,19 +19,19 @@ #ifdef __ASSEMBLY__ -#ifndef AT91_SDRAMC_BASE -#define AT91_SDRAMC_BASE AT91_SDRAMC0_BASE +#ifndef ATMEL_BASE_SDRAMC +#define ATMEL_BASE_SDRAMC AT91_SDRAMC0_BASE #endif -#define AT91_ASM_SDRAMC_MR AT91_SDRAMC_BASE -#define AT91_ASM_SDRAMC_TR (AT91_SDRAMC_BASE + 0x04) -#define AT91_ASM_SDRAMC_CR (AT91_SDRAMC_BASE + 0x08) -#define AT91_ASM_SDRAMC_MDR (AT91_SDRAMC_BASE + 0x24) +#define AT91_ASM_SDRAMC_MR ATMEL_BASE_SDRAMC +#define AT91_ASM_SDRAMC_TR (ATMEL_BASE_SDRAMC + 0x04) +#define AT91_ASM_SDRAMC_CR (ATMEL_BASE_SDRAMC + 0x08) +#define AT91_ASM_SDRAMC_MDR (ATMEL_BASE_SDRAMC + 0x24) #endif /* SDRAM Controller (SDRAMC) registers */ -#define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */ +#define AT91_SDRAMC_MR (ATMEL_BASE_SDRAMC + 0x00) /* SDRAM Controller Mode Register */ #define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */ #define AT91_SDRAMC_MODE_NORMAL 0 #define AT91_SDRAMC_MODE_NOP 1 @@ -41,10 +41,10 @@ #define AT91_SDRAMC_MODE_EXT_LMR 5 #define AT91_SDRAMC_MODE_DEEP 6 -#define AT91_SDRAMC_TR (AT91_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */ +#define AT91_SDRAMC_TR (ATMEL_BASE_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */ #define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */ -#define AT91_SDRAMC_CR (AT91_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */ +#define AT91_SDRAMC_CR (ATMEL_BASE_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */ #define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */ #define AT91_SDRAMC_NC_8 (0 << 0) #define AT91_SDRAMC_NC_9 (1 << 0) @@ -71,7 +71,7 @@ #define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */ #define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */ -#define AT91_SDRAMC_LPR (AT91_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */ +#define AT91_SDRAMC_LPR (ATMEL_BASE_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */ #define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */ #define AT91_SDRAMC_LPCB_DISABLE 0 #define AT91_SDRAMC_LPCB_SELF_REFRESH 1 @@ -85,13 +85,13 @@ #define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12) #define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12) -#define AT91_SDRAMC_IER (AT91_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */ -#define AT91_SDRAMC_IDR (AT91_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */ -#define AT91_SDRAMC_IMR (AT91_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */ -#define AT91_SDRAMC_ISR (AT91_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */ +#define AT91_SDRAMC_IER (ATMEL_BASE_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */ +#define AT91_SDRAMC_IDR (ATMEL_BASE_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */ +#define AT91_SDRAMC_IMR (ATMEL_BASE_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */ +#define AT91_SDRAMC_ISR (ATMEL_BASE_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */ #define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */ -#define AT91_SDRAMC_MDR (AT91_SDRAMC + 0x24) /* SDRAM Memory Device Register */ +#define AT91_SDRAMC_MDR (ATMEL_BASE_SDRAMC + 0x24) /* SDRAM Memory Device Register */ #define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */ #define AT91_SDRAMC_MD_SDRAM 0 #define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1 diff --git a/arch/arm/include/asm/arch-at91/at91sam9_smc.h b/arch/arm/include/asm/arch-at91/at91sam9_smc.h index d180c8a..2ea2791 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9_smc.h +++ b/arch/arm/include/asm/arch-at91/at91sam9_smc.h @@ -18,14 +18,14 @@ #ifdef __ASSEMBLY__ -#ifndef AT91_SMC_BASE -#define AT91_SMC_BASE AT91_SMC0_BASE +#ifndef ATMEL_BASE_SMC +#define ATMEL_BASE_SMC ATMEL_BASE_SMC0 #endif -#define AT91_ASM_SMC_SETUP0 AT91_SMC_BASE -#define AT91_ASM_SMC_PULSE0 (AT91_SMC_BASE + 0x04) -#define AT91_ASM_SMC_CYCLE0 (AT91_SMC_BASE + 0x08) -#define AT91_ASM_SMC_MODE0 (AT91_SMC_BASE + 0x0C) +#define AT91_ASM_SMC_SETUP0 ATMEL_BASE_SMC +#define AT91_ASM_SMC_PULSE0 (ATMEL_BASE_SMC + 0x04) +#define AT91_ASM_SMC_CYCLE0 (ATMEL_BASE_SMC + 0x08) +#define AT91_ASM_SMC_MODE0 (ATMEL_BASE_SMC + 0x0C) #else