diff mbox

[U-Boot,v3,2/2] ftsdmc021: add register definitions of ftsdmc021

Message ID 1303797876-28548-2-git-send-email-macpaul@andestech.com
State Superseded
Delegated to: Macpaul Lin
Headers show

Commit Message

Macpaul Lin April 26, 2011, 6:04 a.m. UTC 
Support registers definitions of ftsdmc021 SDRAM controller.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
---
Changes for v2:
 - Add __ASSEMBLY__ protecton to register offset for supporting lowlevel_init
Changes for v3:
 - Patch: no change. Changed a mail server to resend this.

 include/faraday/ftsdmc021.h |  154 +++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 154 insertions(+), 0 deletions(-)
 create mode 100644 include/faraday/ftsdmc021.h

Comments

Wolfgang Denk April 26, 2011, 7:15 a.m. UTC | #1 
Dear Macpaul Lin,

In message <1303797876-28548-2-git-send-email-macpaul@andestech.com> you wrote:
> Support registers definitions of ftsdmc021 SDRAM controller.
> 
> Signed-off-by: Macpaul Lin <macpaul@andestech.com>
> ---
> Changes for v2:
>  - Add __ASSEMBLY__ protecton to register offset for supporting lowlevel_init
> Changes for v3:
>  - Patch: no change. Changed a mail server to resend this.
...
> +#ifdef __ASSEMBLY__
> +#define FTSDMC021_OFFSET_TP1		0x00	/* SDRAM Timing Parameter 1 */
> +#define FTSDMC021_OFFSET_TP2		0x04	/* SDRAM Timing Parameter 2 */
> +#define FTSDMC021_OFFSET_CR1		0x08	/* SDRAM Configuration Reg 1 */
> +#define FTSDMC021_OFFSET_CR2		0x0C	/* SDRAM Configuration Reg 2 */
> +#define FTSDMC021_OFFSET_BANK0_BSR	0x10	/* External Bank Base/Size Reg 0 */
> +#define FTSDMC021_OFFSET_BANK1_BSR	0x14	/* External Bank Base/Size Reg 1 */
> +#define FTSDMC021_OFFSET_BANK2_BSR	0x18	/* External Bank Base/Size Reg 2 */
> +#define FTSDMC021_OFFSET_BANK3_BSR	0x1C	/* External Bank Base/Size Reg 3 */
> +#define FTSDMC021_OFFSET_BANK4_BSR	0x20	/* External Bank Base/Size Reg 4 */
> +#define FTSDMC021_OFFSET_BANK5_BSR	0x24	/* External Bank Base/Size Reg 5 */
> +#define FTSDMC021_OFFSET_BANK6_BSR	0x28	/* External Bank Base/Size Reg 6 */
> +#define FTSDMC021_OFFSET_BANK7_BSR	0x2C	/* External Bank Base/Size Reg 7 */

Lines too long.  Please fix globally.

I think it is generally wrong to manually define these offsets here.
You should use a C struct instead, and auto-generate the offsets if
needed using the asm-offsets approach (see top level Makefile for
details).

> +/* 12-bit base address of external bank.
> + * Default value is 0x800.
> + * The 12-bit equals to the haddr[31:20] of AHB address bus. */
> +#define FTSDMC021_BANK_BASE(x)		((x) & 0xfff)
> +
> +#define FTSDMC021_BANK_SIZE_1M		0x0
> +#define FTSDMC021_BANK_SIZE_2M		0x1
> +#define FTSDMC021_BANK_SIZE_4M		0x2
> +#define FTSDMC021_BANK_SIZE_8M		0x3
> +#define FTSDMC021_BANK_SIZE_16M		0x4
> +#define FTSDMC021_BANK_SIZE_32M		0x5
> +#define FTSDMC021_BANK_SIZE_64M		0x6
> +#define FTSDMC021_BANK_SIZE_128M	0x7
> +#define FTSDMC021_BANK_SIZE_256M	0x8
> +#define FTSDMC021_BANK_SIZE_512M	0x9

Why don't you use a generic macro here, like

	#define FTSDMC021_BANK_SIZE(sz)	(ffs(x) - 21)

?


Best regards,

Wolfgang Denk
Macpaul Lin April 26, 2011, 7:20 a.m. UTC | #2 
Hi Wolfgang,

2011/4/26 Wolfgang Denk <wd@denx.de>:
> Dear Macpaul Lin,
>> +#define FTSDMC021_OFFSET_BANK7_BSR   0x2C    /* External Bank Base/Size Reg 7 */
>
> Lines too long.  Please fix globally.
>
> I think it is generally wrong to manually define these offsets here.
> You should use a C struct instead, and auto-generate the offsets if
> needed using the asm-offsets approach (see top level Makefile for
> details).

Since this is a patch send before in old times, I will fix it soon and
send the next patch.

>> +#define FTSDMC021_BANK_SIZE_128M     0x7
>> +#define FTSDMC021_BANK_SIZE_256M     0x8
>> +#define FTSDMC021_BANK_SIZE_512M     0x9
>
> Why don't you use a generic macro here, like
>
>        #define FTSDMC021_BANK_SIZE(sz) (ffs(x) - 21)

Thanks for your suggestion.
diff mbox

Patch

diff --git a/include/faraday/ftsdmc021.h b/include/faraday/ftsdmc021.h
new file mode 100644
index 0000000..3ed535a
--- /dev/null
+++ b/include/faraday/ftsdmc021.h
@@ -0,0 +1,154 @@ 
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * (C) Copyright 2011 Andes Technology Corp
+ * Macpaul Lin <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * FTSDMC021 - SDRAM Controller
+ */
+#ifndef __FTSDMC021_H
+#define __FTSDMC021_H
+
+#ifdef __ASSEMBLY__
+#define FTSDMC021_OFFSET_TP1		0x00	/* SDRAM Timing Parameter 1 */
+#define FTSDMC021_OFFSET_TP2		0x04	/* SDRAM Timing Parameter 2 */
+#define FTSDMC021_OFFSET_CR1		0x08	/* SDRAM Configuration Reg 1 */
+#define FTSDMC021_OFFSET_CR2		0x0C	/* SDRAM Configuration Reg 2 */
+#define FTSDMC021_OFFSET_BANK0_BSR	0x10	/* External Bank Base/Size Reg 0 */
+#define FTSDMC021_OFFSET_BANK1_BSR	0x14	/* External Bank Base/Size Reg 1 */
+#define FTSDMC021_OFFSET_BANK2_BSR	0x18	/* External Bank Base/Size Reg 2 */
+#define FTSDMC021_OFFSET_BANK3_BSR	0x1C	/* External Bank Base/Size Reg 3 */
+#define FTSDMC021_OFFSET_BANK4_BSR	0x20	/* External Bank Base/Size Reg 4 */
+#define FTSDMC021_OFFSET_BANK5_BSR	0x24	/* External Bank Base/Size Reg 5 */
+#define FTSDMC021_OFFSET_BANK6_BSR	0x28	/* External Bank Base/Size Reg 6 */
+#define FTSDMC021_OFFSET_BANK7_BSR	0x2C	/* External Bank Base/Size Reg 7 */
+#define FTSDMC021_OFFSET_RAGR		0x30	/* Read Arbitration Group Reg */
+#define FTSDMC021_OFFSET_FRR		0x34	/* Flush Request Register */
+#define FTSDMC021_OFFSET_EBISR		0x38	/* EBI Support Register */
+#define FTSDMC021_OFFSET_CRR		0x100	/* Controller Revision Reg */
+#define FTSDMC021_OFFSET_CFR		0x104	/* Controller Feature Reg */
+#endif /* __ASSEMBLY__ */
+
+/*
+ * Timing Parameter 1 Register
+ */
+#define FTSDMC021_TP1_TCL(x)	((x) & 0x3)
+#define FTSDMC021_TP1_TWR(x)	(((x) & 0x3) << 4)
+#define FTSDMC021_TP1_TRF(x)	(((x) & 0xf) << 8)
+#define FTSDMC021_TP1_TRCD(x)	(((x) & 0x7) << 12)
+#define FTSDMC021_TP1_TRP(x)	(((x) & 0xf) << 16)
+#define FTSDMC021_TP1_TRAS(x)	(((x) & 0xf) << 20)
+
+/*
+ * Timing Parameter 2 Register
+ */
+#define FTSDMC021_TP2_REF_INTV(x)	((x) & 0xffff)
+#define FTSDMC021_TP2_INI_REFT(x)	(((x) & 0xf) << 16)
+#define FTSDMC021_TP2_INI_PREC(x)	(((x) & 0xf) << 20)
+
+/*
+ * Configuration Register 1
+ */
+#define FTSDMC021_CR1_BNKSIZEF(x)	((x) & 0xf)
+#define FTSDMC021_CR1_MBW(x)		(((x) & 0x3) << 4)
+#define FTSDMC021_CR1_DSZ(x)		(((x) & 0x7) << 8)
+#define FTSDMC021_CR1_DDW(x)		(((x) & 0x3) << 12)
+#define FTSDMC021_CR1_MA2T(x)		(1 << 16)	/* Double Memory Address Cycle Enable */
+
+/*
+ * Configuration Register 2
+ */
+#define FTSDMC021_CR2_SREF	(1 << 0)
+#define FTSDMC021_CR2_PWDN	(1 << 1)
+#define FTSDMC021_CR2_ISMR	(1 << 2)
+#define FTSDMC021_CR2_IREF	(1 << 3)
+#define FTSDMC021_CR2_IPREC	(1 << 4)
+#define FTSDMC021_CR2_REFTYPE	(1 << 5)
+
+/*
+ * SDRAM External Bank Base/Size Register
+ */
+#define FTSDMC021_BANK_ENABLE		(1 << 12)
+
+/* 12-bit base address of external bank.
+ * Default value is 0x800.
+ * The 12-bit equals to the haddr[31:20] of AHB address bus. */
+#define FTSDMC021_BANK_BASE(x)		((x) & 0xfff)
+
+#define FTSDMC021_BANK_SIZE_1M		0x0
+#define FTSDMC021_BANK_SIZE_2M		0x1
+#define FTSDMC021_BANK_SIZE_4M		0x2
+#define FTSDMC021_BANK_SIZE_8M		0x3
+#define FTSDMC021_BANK_SIZE_16M		0x4
+#define FTSDMC021_BANK_SIZE_32M		0x5
+#define FTSDMC021_BANK_SIZE_64M		0x6
+#define FTSDMC021_BANK_SIZE_128M	0x7
+#define FTSDMC021_BANK_SIZE_256M	0x8
+#define FTSDMC021_BANK_SIZE_512M	0x9
+
+/*
+ * Read Arbitration Grant Window Register
+ */
+#define FTSDMC021_RAGR_CH1GW(x)		(((x) & 0xff) << 0)
+#define FTSDMC021_RAGR_CH2GW(x)		(((x) & 0xff) << 4)
+#define FTSDMC021_RAGR_CH3GW(x)		(((x) & 0xff) << 8)
+#define FTSDMC021_RAGR_CH4GW(x)		(((x) & 0xff) << 12)
+#define FTSDMC021_RAGR_CH5GW(x)		(((x) & 0xff) << 16)
+#define FTSDMC021_RAGR_CH6GW(x)		(((x) & 0xff) << 20)
+#define FTSDMC021_RAGR_CH7GW(x)		(((x) & 0xff) << 24)
+#define FTSDMC021_RAGR_CH8GW(x)		(((x) & 0xff) << 28)
+
+/*
+ * Flush Request Register
+ */
+#define FTSDMC021_FRR_FLUSHCHN(x)	(((x) & 0x7) << 0)
+#define FTSDMC021_FRR_FLUSHCMPLT	(1 << 3)
+
+/*
+ * External Bus Interface Support Register (EBISR)
+ */
+#define FTSDMC021_EBISR_MR(x)		((x) & 0xfff)
+#define FTSDMC021_EBISR_PRSMR		(1 << 12)
+#define FTSDMC021_EBISR_POPREC		(1 << 13)
+#define FTSDMC021_EBISR_POSMR		(1 << 14)
+
+/*
+ * Controller Revision Register (CRR, Read Only)
+ */
+#define FTSDMC021_CRR_REV_VER		(((x) >> 0) & 0xff)
+#define FTSDMC021_CRR_MINOR_VER		(((x) >> 8) & 0xff)
+#define FTSDMC021_CRR_MAJOR_VER		(((x) >> 16) & 0xff)
+
+/*
+ * Controller Feature Register (CFR, Read Only)
+ */
+#define FTSDMC021_CFR_EBNK		(((x) >> 0) & 0xf)
+#define FTSDMC021_CFR_CHN		(((x) >> 8) & 0xf)
+#define FTSDMC021_CFR_EBI		(((x) >> 16) & 0x1)
+#define FTSDMC021_CFR_CH1_FDEPTH	(((x) >> 24) & 0x1)
+#define FTSDMC021_CFR_CH2_FDEPTH	(((x) >> 25) & 0x1)
+#define FTSDMC021_CFR_CH3_FDEPTH	(((x) >> 26) & 0x1)
+#define FTSDMC021_CFR_CH4_FDEPTH	(((x) >> 27) & 0x1)
+#define FTSDMC021_CFR_CH5_FDEPTH	(((x) >> 28) & 0x1)
+#define FTSDMC021_CFR_CH6_FDEPTH	(((x) >> 29) & 0x1)
+#define FTSDMC021_CFR_CH7_FDEPTH	(((x) >> 30) & 0x1)
+#define FTSDMC021_CFR_CH8_FDEPTH	(((x) >> 31) & 0x1)
+
+#endif	/* __FTSDMC021_H */