From patchwork Tue Apr 19 20:42:39 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Rigby X-Patchwork-Id: 92051 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id CF07CB7008 for ; Wed, 20 Apr 2011 06:43:52 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C789128085; Tue, 19 Apr 2011 22:43:50 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id KhI2xgFcx3ds; Tue, 19 Apr 2011 22:43:50 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5E4482808A; Tue, 19 Apr 2011 22:43:44 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6259B28087 for ; Tue, 19 Apr 2011 22:43:41 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id QNem7npiLi6D for ; Tue, 19 Apr 2011 22:43:40 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-px0-f177.google.com (mail-px0-f177.google.com [209.85.212.177]) by theia.denx.de (Postfix) with ESMTPS id 06C0E28085 for ; Tue, 19 Apr 2011 22:43:38 +0200 (CEST) Received: by pxi10 with SMTP id 10so52713pxi.22 for ; Tue, 19 Apr 2011 13:43:35 -0700 (PDT) Received: by 10.68.19.227 with SMTP id i3mr3350010pbe.303.1303245815553; Tue, 19 Apr 2011 13:43:35 -0700 (PDT) Received: from localhost.localdomain (c-76-23-54-220.hsd1.ut.comcast.net [76.23.54.220]) by mx.google.com with ESMTPS id l8sm152228pbg.54.2011.04.19.13.43.32 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 19 Apr 2011 13:43:34 -0700 (PDT) From: John Rigby To: u-boot@lists.denx.de Date: Tue, 19 Apr 2011 14:42:39 -0600 Message-Id: <1303245762-18077-1-git-send-email-john.rigby@linaro.org> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1301761196-26072-1-git-send-email-john.rigby@linaro.org> References: <1301761196-26072-1-git-send-email-john.rigby@linaro.org> Cc: Rabin Vincent , patches@linaro.org Subject: [U-Boot] [PATCHv4 1/4] Serial: p1011: new vendor init options X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Two new options: CONFIG_PL011_SERIAL_RLCR Some vendor versions of PL011 serial ports (e.g. ST-Ericsson U8500) have separate receive and transmit line control registers. Set this variable to initialize the extra register. CONFIG_PL011_SERIAL_FLUSH_ON_INIT On some platforms (e.g. U8500) U-Boot is loaded by a second stage boot loader that has already initialized the UART. Define this variable to flush the UART at init time. empty fifo on init Signed-off-by: John Rigby Signed-off-by: Rabin Vincent --- v2: No changes v3: Enable changes with new CONFIG_* options instead of platform. Document new CONFIG_* options in README. v4: Added delay before writing to RLCR. Removed Rabin as author at his request. README | 12 ++++++++++++ drivers/serial/serial_pl01x.c | 30 +++++++++++++++++++++++++++--- drivers/serial/serial_pl01x.h | 4 ++++ 3 files changed, 43 insertions(+), 3 deletions(-) diff --git a/README b/README index 4917e26..496a428 100644 --- a/README +++ b/README @@ -468,6 +468,18 @@ The following options need to be configured: define this to a list of base addresses for each (supported) port. See e.g. include/configs/versatile.h + CONFIG_PL011_SERIAL_RLCR + + Some vendor versions of PL011 serial ports (e.g. ST-Ericsson U8500) + have separate receive and transmit line control registers. Set + this variable to initialize the extra register. + + CONFIG_PL011_SERIAL_FLUSH_ON_INIT + + On some platforms (e.g. U8500) U-Boot is loaded by a second stage + boot loader that has already initialized the UART. Define this + variable to flush the UART at init time. + - Console Interface: Depending on board, define exactly one serial port diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c index 5dfcde8..7a064ff 100644 --- a/drivers/serial/serial_pl01x.c +++ b/drivers/serial/serial_pl01x.c @@ -111,6 +111,15 @@ int serial_init (void) unsigned int divider; unsigned int remainder; unsigned int fraction; + unsigned int lcr; + +#ifdef CONFIG_PL011_SERIAL_FLUSH_ON_INIT + /* Empty RX fifo if necessary */ + if (readl(®s->pl011_cr) & UART_PL011_CR_UARTEN) { + while (!(readl(®s->fr) & UART_PL01x_FR_RXFE)) + readl(®s->dr); + } +#endif /* First, disable everything */ writel(0, ®s->pl011_cr); @@ -131,9 +140,24 @@ int serial_init (void) writel(fraction, ®s->pl011_fbrd); /* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */ - writel(UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN, - ®s->pl011_lcrh); - + lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN; + writel(lcr, ®s->pl011_lcrh); + +#ifdef CONFIG_PL011_SERIAL_RLCR + { + int i; + + /* + * Program receive line control register after waiting + * 10 bus cycles. Delay be writing to readonly register + * 10 times + */ + for (i = 0; i < 10; i++) + writel(lcr, ®s->fr); + + writel(lcr, ®s->pl011_rlcr); + } +#endif /* Finally, enable the UART */ writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | UART_PL011_CR_RXE, ®s->pl011_cr); diff --git a/drivers/serial/serial_pl01x.h b/drivers/serial/serial_pl01x.h index b670c24..96ee381 100644 --- a/drivers/serial/serial_pl01x.h +++ b/drivers/serial/serial_pl01x.h @@ -43,7 +43,11 @@ struct pl01x_regs { u32 pl010_lcrl; /* 0x10 Line control register, low byte */ u32 pl010_cr; /* 0x14 Control register */ u32 fr; /* 0x18 Flag register (Read only) */ +#ifdef CONFIG_PL011_SERIAL_RLCR + u32 pl011_rlcr; /* 0x1c Receive line control register */ +#else u32 reserved; +#endif u32 ilpr; /* 0x20 IrDA low-power counter register */ u32 pl011_ibrd; /* 0x24 Integer baud rate register */ u32 pl011_fbrd; /* 0x28 Fractional baud rate register */