From patchwork Thu Apr 14 22:09:39 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Warren X-Patchwork-Id: 91306 X-Patchwork-Delegate: albert.aribaud@free.fr Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id EDD91B6F7B for ; Fri, 15 Apr 2011 08:10:05 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D1FCC283A8; Fri, 15 Apr 2011 00:10:03 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id rlah1KDfxOZa; Fri, 15 Apr 2011 00:10:03 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 17BB628375; Fri, 15 Apr 2011 00:10:02 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B63BF282E7 for ; Fri, 15 Apr 2011 00:09:59 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id A2ofk9ZL1O17 for ; Fri, 15 Apr 2011 00:09:57 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pv0-f172.google.com (mail-pv0-f172.google.com [74.125.83.172]) by theia.denx.de (Postfix) with ESMTPS id 06C02282E2 for ; Fri, 15 Apr 2011 00:09:55 +0200 (CEST) Received: by pvh1 with SMTP id 1so791264pvh.3 for ; Thu, 14 Apr 2011 15:09:53 -0700 (PDT) Received: by 10.68.50.161 with SMTP id d1mr852966pbo.439.1302818993797; Thu, 14 Apr 2011 15:09:53 -0700 (PDT) Received: from localhost.localdomain (ip70-190-110-83.ph.ph.cox.net [70.190.110.83]) by mx.google.com with ESMTPS id i5sm5208pbe.55.2011.04.14.15.09.52 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 14 Apr 2011 15:09:53 -0700 (PDT) From: Tom Warren To: u-boot@lists.denx.de Date: Thu, 14 Apr 2011 15:09:39 -0700 Message-Id: <1302818981-28270-2-git-send-email-twarren@nvidia.com> X-Mailer: git-send-email 1.7.4.3 In-Reply-To: <1302818981-28270-1-git-send-email-twarren@nvidia.com> References: <1302818981-28270-1-git-send-email-twarren@nvidia.com> Cc: twarren.nvidia@gmail.com, Tom Warren Subject: [U-Boot] [PATCH V2 1/3] arm: Tegra2: Add missing PLLX init X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Signed-off-by: Tom Warren --- arch/arm/cpu/armv7/tegra2/ap20.c | 29 ++++++++++++++++++++++++++++ arch/arm/include/asm/arch-tegra2/clk_rst.h | 6 +++- 2 files changed, 33 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c b/arch/arm/cpu/armv7/tegra2/ap20.c index d3e6797..60dd5df 100644 --- a/arch/arm/cpu/armv7/tegra2/ap20.c +++ b/arch/arm/cpu/armv7/tegra2/ap20.c @@ -32,6 +32,32 @@ u32 s_first_boot = 1; +void init_pllx(void) +{ + struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + u32 reg; + + /* If PLLX is already enabled, just return */ + reg = readl(&clkrst->crc_pllx_base); + if (reg & PLL_ENABLE) + return; + + /* Set PLLX_MISC */ + reg = CPCON; /* CPCON[11:8] = 0001 */ + writel(reg, &clkrst->crc_pllx_misc); + + /* Use 12MHz clock here */ + reg = (PLL_BYPASS | PLL_DIVM); + reg |= (1000 << 8); /* DIVN = 0x3E8 */ + writel(reg, &clkrst->crc_pllx_base); + + reg |= PLL_ENABLE; + writel(reg, &clkrst->crc_pllx_base); + + reg &= ~PLL_BYPASS; + writel(reg, &clkrst->crc_pllx_base); +} + static void enable_cpu_clock(int enable) { struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; @@ -47,6 +73,9 @@ static void enable_cpu_clock(int enable) */ if (enable) { + /* Initialize PLLX */ + init_pllx(); + /* Wait until all clocks are stable */ udelay(PLL_STABILIZATION_DELAY); diff --git a/arch/arm/include/asm/arch-tegra2/clk_rst.h b/arch/arm/include/asm/arch-tegra2/clk_rst.h index d67a5d7..bd8ad2c 100644 --- a/arch/arm/include/asm/arch-tegra2/clk_rst.h +++ b/arch/arm/include/asm/arch-tegra2/clk_rst.h @@ -160,8 +160,8 @@ struct clk_rst_ctlr { #define PLL_DIVP (1 << 20) /* post divider, b22:20 */ #define PLL_DIVM 0x0C /* input divider, b4:0 */ -#define SWR_UARTD_RST (1 << 2) -#define CLK_ENB_UARTD (1 << 2) +#define SWR_UARTD_RST (1 << 1) +#define CLK_ENB_UARTD (1 << 1) #define SWR_UARTA_RST (1 << 6) #define CLK_ENB_UARTA (1 << 6) @@ -189,4 +189,6 @@ struct clk_rst_ctlr { #define CPU0_CLK_STP (1 << 8) #define CPU1_CLK_STP (1 << 9) +#define CPCON (1 << 8) + #endif /* CLK_RST_H */