From patchwork Sat Apr 9 17:49:37 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kumar Gala X-Patchwork-Id: 90470 X-Patchwork-Delegate: galak@kernel.crashing.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 55AA1B6F1B for ; Sun, 10 Apr 2011 03:50:03 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 78063280C4; Sat, 9 Apr 2011 19:49:53 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id NX-GwJue3Yzm; Sat, 9 Apr 2011 19:49:53 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 553F1280AC; Sat, 9 Apr 2011 19:49:49 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 719AF2808A for ; Sat, 9 Apr 2011 19:49:45 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id XJzg7ZjuMrSE for ; Sat, 9 Apr 2011 19:49:43 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) by theia.denx.de (Postfix) with ESMTPS id 08B002808C for ; Sat, 9 Apr 2011 19:49:41 +0200 (CEST) Received: from localhost (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id p39Hnbom027865; Sat, 9 Apr 2011 12:49:37 -0500 From: Kumar Gala To: u-boot@lists.denx.de Date: Sat, 9 Apr 2011 12:49:37 -0500 Message-Id: <1302371377-11032-1-git-send-email-galak@kernel.crashing.org> X-Mailer: git-send-email 1.5.6.5 Cc: Dipen Dudhat Subject: [U-Boot] [PATCH] powerpc/85xx: Added PMUXCR1 and PMUXCR2 defines for P1010/P1014 SoC X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Dipen Dudhat Signed-off-by: Dipen Dudhat Signed-off-by: Kumar Gala --- arch/powerpc/include/asm/immap_85xx.h | 71 +++++++++++++++++++++++++++++++++ 1 files changed, 71 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 5ad9787..d6ac61a 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1920,6 +1920,52 @@ typedef struct ccsr_gur { u32 gpindr; /* General-purpose input data */ u8 res5[12]; u32 pmuxcr; /* Alt. function signal multiplex control */ +#if defined(CONFIG_P1010) || defined(CONFIG_P1014) +#define MPC85xx_PMUXCR_TSEC1_0_1588 0x40000000 +#define MPC85xx_PMUXCR_TSEC1_0_RES 0xC0000000 +#define MPC85xx_PMUXCR_TSEC1_1_1588_TRIG 0x10000000 +#define MPC85xx_PMUXCR_TSEC1_1_GPIO_12 0x20000000 +#define MPC85xx_PMUXCR_TSEC1_1_RES 0x30000000 +#define MPC85xx_PMUXCR_TSEC1_2_DMA 0x04000000 +#define MPC85xx_PMUXCR_TSEC1_2_GPIO 0x08000000 +#define MPC85xx_PMUXCR_TSEC1_2_RES 0x0C000000 +#define MPC85xx_PMUXCR_TSEC1_3_RES 0x01000000 +#define MPC85xx_PMUXCR_TSEC1_3_GPIO_15 0x02000000 +#define MPC85xx_PMUXCR_IFC_ADDR16_SDHC 0x00400000 +#define MPC85xx_PMUXCR_IFC_ADDR16_USB 0x00800000 +#define MPC85xx_PMUXCR_IFC_ADDR16_IFC_CS2 0x00C00000 +#define MPC85xx_PMUXCR_IFC_ADDR17_18_SDHC 0x00100000 +#define MPC85xx_PMUXCR_IFC_ADDR17_18_USB 0x00200000 +#define MPC85xx_PMUXCR_IFC_ADDR17_18_DMA 0x00300000 +#define MPC85xx_PMUXCR_IFC_ADDR19_SDHC_DATA 0x00040000 +#define MPC85xx_PMUXCR_IFC_ADDR19_USB 0x00080000 +#define MPC85xx_PMUXCR_IFC_ADDR19_DMA 0x000C0000 +#define MPC85xx_PMUXCR_IFC_ADDR20_21_SDHC_DATA 0x00010000 +#define MPC85xx_PMUXCR_IFC_ADDR20_21_USB 0x00020000 +#define MPC85xx_PMUXCR_IFC_ADDR20_21_RES 0x00030000 +#define MPC85xx_PMUXCR_IFC_ADDR22_SDHC 0x00004000 +#define MPC85xx_PMUXCR_IFC_ADDR22_USB 0x00008000 +#define MPC85xx_PMUXCR_IFC_ADDR22_RES 0x0000C000 +#define MPC85xx_PMUXCR_IFC_ADDR23_SDHC 0x00001000 +#define MPC85xx_PMUXCR_IFC_ADDR23_USB 0x00002000 +#define MPC85xx_PMUXCR_IFC_ADDR23_RES 0x00003000 +#define MPC85xx_PMUXCR_IFC_ADDR24_SDHC 0x00000400 +#define MPC85xx_PMUXCR_IFC_ADDR24_USB 0x00000800 +#define MPC85xx_PMUXCR_IFC_ADDR24_RES 0x00000C00 +#define MPC85xx_PMUXCR_IFC_PAR_PERR_RES 0x00000300 +#define MPC85xx_PMUXCR_IFC_PAR_PERR_USB 0x00000200 +#define MPC85xx_PMUXCR_LCLK_RES 0x00000040 +#define MPC85xx_PMUXCR_LCLK_USB 0x00000080 +#define MPC85xx_PMUXCR_LCLK_IFC_CS3 0x000000C0 +#define MPC85xx_PMUXCR_SPI_RES 0x00000030 +#define MPC85xx_PMUXCR_SPI_GPIO 0x00000020 +#define MPC85xx_PMUXCR_CAN1_UART 0x00000004 +#define MPC85xx_PMUXCR_CAN1_TDM 0x00000008 +#define MPC85xx_PMUXCR_CAN1_RES 0x0000000C +#define MPC85xx_PMUXCR_CAN2_UART 0x00000001 +#define MPC85xx_PMUXCR_CAN2_TDM 0x00000002 +#define MPC85xx_PMUXCR_CAN2_RES 0x00000003 +#endif #define MPC85xx_PMUXCR_SD_DATA 0x80000000 #define MPC85xx_PMUXCR_SDHC_CD 0x40000000 #define MPC85xx_PMUXCR_SDHC_WP 0x20000000 @@ -1945,6 +1991,31 @@ typedef struct ccsr_gur { #define MPC85xx_PMUXCR_SPI 0x00000000 #endif u32 pmuxcr2; /* Alt. function signal multiplex control 2 */ +#if defined(CONFIG_P1010) || defined(CONFIG_P1014) +#define MPC85xx_PMUXCR2_UART_GPIO 0x40000000 +#define MPC85xx_PMUXCR2_UART_TDM 0x80000000 +#define MPC85xx_PMUXCR2_UART_RES 0xC0000000 +#define MPC85xx_PMUXCR2_IRQ2_TRIG_IN 0x10000000 +#define MPC85xx_PMUXCR2_IRQ2_RES 0x30000000 +#define MPC85xx_PMUXCR2_IRQ3_SRESET 0x04000000 +#define MPC85xx_PMUXCR2_IRQ3_RES 0x0C000000 +#define MPC85xx_PMUXCR2_GPIO01_DRVVBUS 0x01000000 +#define MPC85xx_PMUXCR2_GPIO01_RES 0x03000000 +#define MPC85xx_PMUXCR2_GPIO23_CKSTP 0x00400000 +#define MPC85xx_PMUXCR2_GPIO23_RES 0x00800000 +#define MPC85xx_PMUXCR2_GPIO23_USB 0x00C00000 +#define MPC85xx_PMUXCR2_GPIO4_MCP 0x00100000 +#define MPC85xx_PMUXCR2_GPIO4_RES 0x00200000 +#define MPC85xx_PMUXCR2_GPIO4_CLK_OUT 0x00300000 +#define MPC85xx_PMUXCR2_GPIO5_UDE 0x00040000 +#define MPC85xx_PMUXCR2_GPIO5_RES 0x00080000 +#define MPC85xx_PMUXCR2_READY_ASLEEP 0x00020000 +#define MPC85xx_PMUXCR2_DDR_ECC_MUX 0x00010000 +#define MPC85xx_PMUXCR2_DEBUG_PORT_EXPOSE 0x00008000 +#define MPC85xx_PMUXCR2_POST_EXPOSE 0x00004000 +#define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY 0x00002000 +#define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE 0x00001000 +#endif #if defined(CONFIG_P1013) || defined(CONFIG_P1022) #define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f1000 #define MPC85xx_PMUXCR2_USB 0x00150000