From patchwork Thu Mar 10 22:09:26 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Tyser X-Patchwork-Id: 86338 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 9113BB6FB1 for ; Fri, 11 Mar 2011 09:09:49 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A31CE28098; Thu, 10 Mar 2011 23:09:46 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ihiV2pHCLm8K; Thu, 10 Mar 2011 23:09:46 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DF0582808F; Thu, 10 Mar 2011 23:09:44 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4BD252808F for ; Thu, 10 Mar 2011 23:09:42 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id yMFlYkIZni3e for ; Thu, 10 Mar 2011 23:09:41 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from xes-mad.com (xes-mad.com [216.165.139.218]) by theia.denx.de (Postfix) with ESMTPS id 1C43A2808D for ; Thu, 10 Mar 2011 23:09:38 +0100 (CET) Received: from localhost.localdomain (petert [10.52.0.62]) by xes-mad.com (8.13.8/8.13.8) with ESMTP id p2AM9TLI031539; Thu, 10 Mar 2011 16:09:30 -0600 From: Peter Tyser To: u-boot@lists.denx.de Date: Thu, 10 Mar 2011 16:09:26 -0600 Message-Id: <1299794966-32040-1-git-send-email-ptyser@xes-inc.com> X-Mailer: git-send-email 1.7.0.4 X-Virus-Scanned: clamav-milter 0.96 at mail X-Virus-Status: Clean Cc: Peter Tyser , galak@kernel.crashing.org Subject: [U-Boot] [PATCH] mpc8[5/6]xx: Ensure POST word does not get reset X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: John Schmoller The POST word is stored in a spare register in the PIC on MPC8[5/6]xx processors. When interrupt_init() is called, this register gets reset which resulted in all POST_RAM POSTs not being ran due to the corrupted POST word. To resolve this, store off POST word before the PIC is reset, and restore it after the PIC has been initialized. Signed-off-by: John Schmoller Signed-off-by: Peter Tyser --- This is a bugfix, so it'd be nice if it made it into the upcoming release if possible. arch/powerpc/cpu/mpc85xx/interrupts.c | 16 ++++++++++++++++ arch/powerpc/cpu/mpc86xx/interrupts.c | 16 ++++++++++++++++ 2 files changed, 32 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/interrupts.c b/arch/powerpc/cpu/mpc85xx/interrupts.c index a62b031..7ab7113 100644 --- a/arch/powerpc/cpu/mpc85xx/interrupts.c +++ b/arch/powerpc/cpu/mpc85xx/interrupts.c @@ -32,11 +32,23 @@ #include #include #include +#ifdef CONFIG_POST +#include +#endif int interrupt_init_cpu(unsigned int *decrementer_count) { ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR; +#ifdef CONFIG_POST + /* + * The POST word is stored in the PIC's TFRR register which gets + * cleared when the PIC is reset. Save it off so we can restore it + * later. + */ + ulong post_word = post_word_load(); +#endif + out_be32(&pic->gcr, MPC85xx_PICGCR_RST); while (in_be32(&pic->gcr) & MPC85xx_PICGCR_RST) ; @@ -78,6 +90,10 @@ int interrupt_init_cpu(unsigned int *decrementer_count) pic->ctpr=0; /* 40080 clear current task priority register */ #endif +#ifdef CONFIG_POST + post_word_store(post_word); +#endif + return (0); } diff --git a/arch/powerpc/cpu/mpc86xx/interrupts.c b/arch/powerpc/cpu/mpc86xx/interrupts.c index d8ad6d3..14821f4 100644 --- a/arch/powerpc/cpu/mpc86xx/interrupts.c +++ b/arch/powerpc/cpu/mpc86xx/interrupts.c @@ -35,12 +35,24 @@ #include #include #include +#ifdef CONFIG_POST +#include +#endif int interrupt_init_cpu(unsigned long *decrementer_count) { volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; volatile ccsr_pic_t *pic = &immr->im_pic; +#ifdef CONFIG_POST + /* + * The POST word is stored in the PIC's TFRR register which gets + * cleared when the PIC is reset. Save it off so we can restore it + * later. + */ + ulong post_word = post_word_load(); +#endif + pic->gcr = MPC86xx_PICGCR_RST; while (pic->gcr & MPC86xx_PICGCR_RST) ; @@ -74,6 +86,10 @@ int interrupt_init_cpu(unsigned long *decrementer_count) pic->ctpr = 0; /* 40080 clear current task priority register */ #endif +#ifdef CONFIG_POST + post_word_store(post_word); +#endif + return 0; }