From patchwork Thu Mar 10 19:26:22 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Estevam X-Patchwork-Id: 86332 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 132E6B6FB0 for ; Fri, 11 Mar 2011 06:16:15 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 643AE28084; Thu, 10 Mar 2011 20:16:12 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id CqftJLLGifrG; Thu, 10 Mar 2011 20:16:12 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D384D28091; Thu, 10 Mar 2011 20:16:09 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BAE2C28091 for ; Thu, 10 Mar 2011 20:16:07 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id PATULSwpVjmH for ; Thu, 10 Mar 2011 20:16:06 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from ch1outboundpool.messaging.microsoft.com (ch1outboundpool.messaging.microsoft.com [216.32.181.185]) by theia.denx.de (Postfix) with ESMTPS id 1986228084 for ; Thu, 10 Mar 2011 20:16:03 +0100 (CET) Received: from mail162-ch1-R.bigfish.com (216.32.181.173) by CH1EHSOBE004.bigfish.com (10.43.70.54) with Microsoft SMTP Server id 14.1.225.8; Thu, 10 Mar 2011 19:16:02 +0000 Received: from mail162-ch1 (localhost.localdomain [127.0.0.1]) by mail162-ch1-R.bigfish.com (Postfix) with ESMTP id 393BD1010310; Thu, 10 Mar 2011 19:16:02 +0000 (UTC) X-SpamScore: 3 X-BigFish: VS3(zzc8kzz1202hzz8275bhz2dh2a8h668h61h) X-Spam-TCS-SCL: 0:0 X-Forefront-Antispam-Report: KIP:(null); UIP:(null); IPVD:NLI; H:mail.freescale.net; RD:none; EFVD:NLI Received: from mail162-ch1 (localhost.localdomain [127.0.0.1]) by mail162-ch1 (MessageSwitch) id 1299784561923048_13809; Thu, 10 Mar 2011 19:16:01 +0000 (UTC) Received: from CH1EHSMHS002.bigfish.com (snatpool1.int.messaging.microsoft.com [10.43.68.240]) by mail162-ch1.bigfish.com (Postfix) with ESMTP id D5057155004C; Thu, 10 Mar 2011 19:16:01 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CH1EHSMHS002.bigfish.com (10.43.70.2) with Microsoft SMTP Server (TLS) id 14.1.225.22; Thu, 10 Mar 2011 19:16:00 +0000 Received: from az33smr01.freescale.net (10.64.34.199) by 039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP Server id 14.1.270.2; Thu, 10 Mar 2011 13:15:59 -0600 Received: from localhost.localdomain ([10.29.240.182]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id p2AJFvZf010541; Thu, 10 Mar 2011 13:15:57 -0600 (CST) From: Fabio Estevam To: Date: Thu, 10 Mar 2011 16:26:22 -0300 Message-ID: <1299785182-14534-1-git-send-email-fabio.estevam@freescale.com> X-Mailer: git-send-email 1.6.0.4 MIME-Version: 1.0 X-OriginatorOrg: freescale.com Cc: Fabio Estevam Subject: [U-Boot] [PATCH] ARM: mx31: Print the silicon version X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Use the same method of the Linux kernel to print the MX31 silicon version on boot. Tested on a MX31PDK with a 2.0 silicon, where it shows: CPU: Freescale i.MX31 at 531 MHz MX31 silicon rev 2.0 Signed-off-by: Fabio Estevam --- arch/arm/cpu/arm1136/mx31/generic.c | 18 ++++++++++++ arch/arm/include/asm/arch-mx31/mx31-regs.h | 4 ++ arch/arm/include/asm/imx_soc_revision.h | 42 ++++++++++++++++++++++++++++ 3 files changed, 64 insertions(+), 0 deletions(-) create mode 100644 arch/arm/include/asm/imx_soc_revision.h diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c index 8bd23ee..4791449 100644 --- a/arch/arm/cpu/arm1136/mx31/generic.c +++ b/arch/arm/cpu/arm1136/mx31/generic.c @@ -24,6 +24,7 @@ #include #include #include +#include static u32 mx31_decode_pll(u32 reg, u32 infreq) { @@ -106,11 +107,28 @@ void mx31_set_pad(enum iomux_pins pin, u32 config) } +void mx31_read_cpu_rev(void) +{ + u32 i, srev; + + /* read SREV register from IIM module */ + srev = __raw_readl(MX31_IIM_BASE_ADDR + MXC_IIMSREV); + + for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++) + if (srev == mx31_cpu_type[i].srev) { + printf("MX31 silicon rev %s\n", mx31_cpu_type[i].v); + return; + } + + printf("Unknown CPU identifier. srev = %02x\n", srev); +} + #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo (void) { printf("CPU: Freescale i.MX31 at %d MHz\n", mx31_get_mcu_main_clk() / 1000000); + mx31_read_cpu_rev(); return 0; } #endif diff --git a/arch/arm/include/asm/arch-mx31/mx31-regs.h b/arch/arm/include/asm/arch-mx31/mx31-regs.h index 37337f2..cc0ffc8 100644 --- a/arch/arm/include/asm/arch-mx31/mx31-regs.h +++ b/arch/arm/include/asm/arch-mx31/mx31-regs.h @@ -480,6 +480,10 @@ enum iomux_pins { #define CCMR_FPM (1 << 1) #define CCMR_CKIH (2 << 1) +#define MX31_SPBA0_BASE_ADDR 0x50000000 +#define MX31_IIM_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x1c000) +#define MXC_IIMSREV 0x0024 + #define PDR0_CSI_PODF(x) (((x) & 0x1ff) << 23) #define PDR0_PER_PODF(x) (((x) & 0x1f) << 16) #define PDR0_HSP_PODF(x) (((x) & 0x7) << 11) diff --git a/arch/arm/include/asm/imx_soc_revision.h b/arch/arm/include/asm/imx_soc_revision.h new file mode 100644 index 0000000..01219c6 --- /dev/null +++ b/arch/arm/include/asm/imx_soc_revision.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * + * Fabio Estevam + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation; + */ + +#define IMX_CHIP_REVISION_1_0 0x10 +#define IMX_CHIP_REVISION_1_1 0x11 +#define IMX_CHIP_REVISION_1_2 0x12 +#define IMX_CHIP_REVISION_1_3 0x13 +#define IMX_CHIP_REVISION_2_0 0x20 +#define IMX_CHIP_REVISION_2_1 0x21 +#define IMX_CHIP_REVISION_2_2 0x22 +#define IMX_CHIP_REVISION_2_3 0x23 +#define IMX_CHIP_REVISION_3_0 0x30 +#define IMX_CHIP_REVISION_3_1 0x31 +#define IMX_CHIP_REVISION_3_2 0x32 +#define IMX_CHIP_REVISION_3_3 0x33 +#define IMX_CHIP_REVISION_UNKNOWN 0xff + +struct mx3_cpu_type { + u8 srev; + const char *name; + const char *v; + unsigned int rev; +}; + +struct mx3_cpu_type mx31_cpu_type[] = { + { .srev = 0x00, .name = "i.MX31(L)", .v = "1.0", .rev = IMX_CHIP_REVISION_1_0 }, + { .srev = 0x10, .name = "i.MX31", .v = "1.1", .rev = IMX_CHIP_REVISION_1_1 }, + { .srev = 0x11, .name = "i.MX31L", .v = "1.1", .rev = IMX_CHIP_REVISION_1_1 }, + { .srev = 0x12, .name = "i.MX31", .v = "1.15", .rev = IMX_CHIP_REVISION_1_1 }, + { .srev = 0x13, .name = "i.MX31L", .v = "1.15", .rev = IMX_CHIP_REVISION_1_1 }, + { .srev = 0x14, .name = "i.MX31", .v = "1.2", .rev = IMX_CHIP_REVISION_1_2 }, + { .srev = 0x15, .name = "i.MX31L", .v = "1.2", .rev = IMX_CHIP_REVISION_1_2 }, + { .srev = 0x28, .name = "i.MX31", .v = "2.0", .rev = IMX_CHIP_REVISION_2_0 }, + { .srev = 0x29, .name = "i.MX31L", .v = "2.0", .rev = IMX_CHIP_REVISION_2_0 }, +};