From patchwork Fri Feb 18 12:50:02 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reinhard Meyer X-Patchwork-Id: 83576 X-Patchwork-Delegate: info@emk-elektronik.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 976B1B70F4 for ; Fri, 18 Feb 2011 23:17:04 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D9488280F5; Fri, 18 Feb 2011 13:16:48 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ewkgAnQhem1i; Fri, 18 Feb 2011 13:16:48 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 052852808B; Fri, 18 Feb 2011 13:16:17 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id F342D28088 for ; Fri, 18 Feb 2011 13:16:13 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id YM2NNlbM1skj for ; Fri, 18 Feb 2011 13:16:13 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from moutng.kundenserver.de (moutng.kundenserver.de [212.227.17.9]) by theia.denx.de (Postfix) with ESMTP id 3AB9D2808B for ; Fri, 18 Feb 2011 13:16:00 +0100 (CET) Received: from localhost.localdomain (p5B201A57.dip0.t-ipconnect.de [91.32.26.87]) by mrelayeu.kundenserver.de (node=mrbap1) with ESMTP (Nemesis) id 0Lb92n-1QWagM38Ez-00kMBW; Fri, 18 Feb 2011 13:15:56 +0100 From: Reinhard Meyer To: u-boot@lists.denx.de Date: Fri, 18 Feb 2011 13:50:02 +0100 Message-Id: <1298033414-11481-5-git-send-email-u-boot@emk-elektronik.de> X-Mailer: git-send-email 1.5.6.5 In-Reply-To: <1298033414-11481-4-git-send-email-u-boot@emk-elektronik.de> References: <1298033414-11481-1-git-send-email-u-boot@emk-elektronik.de> <1298033414-11481-2-git-send-email-u-boot@emk-elektronik.de> <1298033414-11481-3-git-send-email-u-boot@emk-elektronik.de> <1298033414-11481-4-git-send-email-u-boot@emk-elektronik.de> X-Provags-ID: V02:K0:DUhytV7WhvE/8zSqMYc3MK6GHLt9742ur8UhhJKflAQ QRkzZy6YPlc83rModnTdjIA3vmj7CNIXFTpmrjz1mh4un/KcYP q6rgXDP1rPn/Cu6gnwMIv5drHuhYMdqTZXm9S0KJLK5rFmeeVr cuxPWqccDfR9Bq57Xz65Ynh8XKDT1641kOpIJPsCDE5vcwekDk bv8t3wx1NLO/EUQFI6C7h4f7sy6pPLxDO2hYtDhEZM= Subject: [U-Boot] [PATCH 04/15] AT91: rework at91sam9g45.h X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Signed-off-by: Reinhard Meyer --- arch/arm/include/asm/arch-at91/at91sam9g45.h | 225 ++++++++++++-------------- 1 files changed, 107 insertions(+), 118 deletions(-) diff --git a/arch/arm/include/asm/arch-at91/at91sam9g45.h b/arch/arm/include/asm/arch-at91/at91sam9g45.h index 445f4b2..364b86c 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9g45.h +++ b/arch/arm/include/asm/arch-at91/at91sam9g45.h @@ -1,10 +1,10 @@ /* * Chip-specific header file for the AT91SAM9M1x family * - * Copyright (C) 2008 Atmel Corporation. + * (C) 2008 Atmel Corporation. * - * Common definitions. - * Based on AT91SAM9G45 preliminary datasheet. + * Definitions for the SoC: + * AT91SAM9G45 * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,137 +16,126 @@ #define AT91SAM9G45_H /* - * Peripheral identifiers/interrupts. + * defines to be used in other places */ -#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define AT91_ID_SYS 1 /* System Controller Interrupt */ -#define AT91SAM9G45_ID_PIOA 2 /* Parallel I/O Controller A */ -#define AT91SAM9G45_ID_PIOB 3 /* Parallel I/O Controller B */ -#define AT91SAM9G45_ID_PIOC 4 /* Parallel I/O Controller C */ -#define AT91SAM9G45_ID_PIODE 5 /* Parallel I/O Controller D and E */ -#define AT91SAM9G45_ID_TRNG 6 /* True Random Number Generator */ -#define AT91SAM9G45_ID_US0 7 /* USART 0 */ -#define AT91SAM9G45_ID_US1 8 /* USART 1 */ -#define AT91SAM9G45_ID_US2 9 /* USART 2 */ -#define AT91SAM9G45_ID_US3 10 /* USART 3 */ -#define AT91SAM9G45_ID_MCI0 11 /* High Speed Multimedia Card Interface 0 */ -#define AT91SAM9G45_ID_TWI0 12 /* Two-Wire Interface 0 */ -#define AT91SAM9G45_ID_TWI1 13 /* Two-Wire Interface 1 */ -#define AT91SAM9G45_ID_SPI0 14 /* Serial Peripheral Interface 0 */ -#define AT91SAM9G45_ID_SPI1 15 /* Serial Peripheral Interface 1 */ -#define AT91SAM9G45_ID_SSC0 16 /* Synchronous Serial Controller 0 */ -#define AT91SAM9G45_ID_SSC1 17 /* Synchronous Serial Controller 1 */ -#define AT91SAM9G45_ID_TCB 18 /* Timer Counter 0, 1, 2, 3, 4 and 5 */ -#define AT91SAM9G45_ID_PWMC 19 /* Pulse Width Modulation Controller */ -#define AT91SAM9G45_ID_TSC 20 /* Touch Screen ADC Controller */ -#define AT91SAM9G45_ID_DMA 21 /* DMA Controller */ -#define AT91SAM9G45_ID_UHPHS 22 /* USB Host High Speed */ -#define AT91SAM9G45_ID_LCDC 23 /* LCD Controller */ -#define AT91SAM9G45_ID_AC97C 24 /* AC97 Controller */ -#define AT91SAM9G45_ID_EMAC 25 /* Ethernet MAC */ -#define AT91SAM9G45_ID_ISI 26 /* Image Sensor Interface */ -#define AT91SAM9G45_ID_UDPHS 27 /* USB Device High Speed */ -#define AT91SAM9G45_ID_AESTDESSHA 28 /* AES + T-DES + SHA */ -#define AT91SAM9G45_ID_MCI1 29 /* High Speed Multimedia Card Interface 1 */ -#define AT91SAM9G45_ID_VDEC 30 /* Video Decoder */ -#define AT91SAM9G45_ID_IRQ0 31 /* Advanced Interrupt Controller */ - -#define AT91_EMAC_BASE 0xfffbc000 -#define AT91_SMC_BASE 0xffffe800 -#define AT91_MATRIX_BASE 0xffffea00 -#define AT91_PIO_BASE 0xfffff200 -#define AT91_PMC_BASE 0xfffffc00 -#define AT91_RSTC_BASE 0xfffffd00 -#define AT91_PIT_BASE 0xfffffd30 -#define AT91_WDT_BASE 0xfffffd40 - -#ifdef CONFIG_AT91_LEGACY +#define CONFIG_ARM926EJS /* ARM926EJS Core */ +#define CONFIG_AT91FAMILY /* it's a member of AT91 */ /* - * User Peripheral physical base addresses. + * Peripheral identifiers/interrupts. */ -#define AT91SAM9G45_BASE_UDPHS 0xfff78000 -#define AT91SAM9G45_BASE_TC0 0xfff7c000 -#define AT91SAM9G45_BASE_TC1 0xfff7c040 -#define AT91SAM9G45_BASE_TC2 0xfff7c080 -#define AT91SAM9G45_BASE_MCI0 0xfff80000 -#define AT91SAM9G45_BASE_TWI0 0xfff84000 -#define AT91SAM9G45_BASE_TWI1 0xfff88000 -#define AT91SAM9G45_BASE_US0 0xfff8c000 -#define AT91SAM9G45_BASE_US1 0xfff90000 -#define AT91SAM9G45_BASE_US2 0xfff94000 -#define AT91SAM9G45_BASE_US3 0xfff98000 -#define AT91SAM9G45_BASE_SSC0 0xfff9c000 -#define AT91SAM9G45_BASE_SSC1 0xfffa0000 -#define AT91SAM9G45_BASE_SPI0 0xfffa4000 -#define AT91SAM9G45_BASE_SPI1 0xfffa8000 -#define AT91SAM9G45_BASE_AC97C 0xfffac000 -#define AT91SAM9G45_BASE_TSC 0xfffb0000 -#define AT91SAM9G45_BASE_ISI 0xfffb4000 -#define AT91SAM9G45_BASE_PWMC 0xfffb8000 -#define AT91SAM9G45_BASE_EMAC 0xfffbc000 -#define AT91SAM9G45_BASE_AES 0xfffc0000 -#define AT91SAM9G45_BASE_TDES 0xfffc4000 -#define AT91SAM9G45_BASE_SHA 0xfffc8000 -#define AT91SAM9G45_BASE_TRNG 0xfffcc000 -#define AT91SAM9G45_BASE_MCI1 0xfffd0000 -#define AT91SAM9G45_BASE_TC3 0xfffd4000 -#define AT91SAM9G45_BASE_TC4 0xfffd4040 -#define AT91SAM9G45_BASE_TC5 0xfffd4080 -#define AT91_BASE_SYS 0xffffe200 +#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ +#define ATMEL_ID_SYS 1 /* System Controller Interrupt */ +#define ATMEL_ID_PIOA 2 /* Parallel I/O Controller A */ +#define ATMEL_ID_PIOB 3 /* Parallel I/O Controller B */ +#define ATMEL_ID_PIOC 4 /* Parallel I/O Controller C */ +#define ATMEL_ID_PIODE 5 /* Parallel I/O Controller D and E */ +#define ATMEL_ID_TRNG 6 /* True Random Number Generator */ +#define ATMEL_ID_USART0 7 /* USART 0 */ +#define ATMEL_ID_USART1 8 /* USART 1 */ +#define ATMEL_ID_USART2 9 /* USART 2 */ +#define ATMEL_ID_USART3 10 /* USART 3 */ +#define ATMEL_ID_MCI0 11 /* High Speed Multimedia Card Interface 0 */ +#define ATMEL_ID_TWI0 12 /* Two-Wire Interface 0 */ +#define ATMEL_ID_TWI1 13 /* Two-Wire Interface 1 */ +#define ATMEL_ID_SPI0 14 /* Serial Peripheral Interface 0 */ +#define ATMEL_ID_SPI1 15 /* Serial Peripheral Interface 1 */ +#define ATMEL_ID_SSC0 16 /* Synchronous Serial Controller 0 */ +#define ATMEL_ID_SSC1 17 /* Synchronous Serial Controller 1 */ +#define ATMEL_ID_TCB 18 /* Timer Counter 0, 1, 2, 3, 4 and 5 */ +#define ATMEL_ID_PWMC 19 /* Pulse Width Modulation Controller */ +#define ATMEL_ID_TSC 20 /* Touch Screen ADC Controller */ +#define ATMEL_ID_DMA 21 /* DMA Controller */ +#define ATMEL_ID_UHPHS 22 /* USB Host High Speed */ +#define ATMEL_ID_LCDC 23 /* LCD Controller */ +#define ATMEL_ID_AC97C 24 /* AC97 Controller */ +#define ATMEL_ID_EMAC 25 /* Ethernet MAC */ +#define ATMEL_ID_ISI 26 /* Image Sensor Interface */ +#define ATMEL_ID_UDPHS 27 /* USB Device High Speed */ +#define ATMEL_ID_AESTDESSHA 28 /* AES + T-DES + SHA */ +#define ATMEL_ID_MCI1 29 /* High Speed Multimedia Card Interface 1 */ +#define ATMEL_ID_VDEC 30 /* Video Decoder */ +#define ATMEL_ID_IRQ0 31 /* Advanced Interrupt Controller */ /* - * System Peripherals (offset from AT91_BASE_SYS) + * User Peripherals physical base addresses. */ -#define AT91_ECC (0xffffe200 - AT91_BASE_SYS) -#define AT91_DDRSDRC1 (0xffffe400 - AT91_BASE_SYS) -#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) -#define AT91_SMC (0xffffe800 - AT91_BASE_SYS) -#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) -#define AT91_DMA (0xffffec00 - AT91_BASE_SYS) -#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) -#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS) -#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS) -#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS) -#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS) -#define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) -#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) -#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) -#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) -#define AT91_RTC (0xfffffdb0 - AT91_BASE_SYS) - -#define AT91_USART0 AT91SAM9G45_BASE_US0 -#define AT91_USART1 AT91SAM9G45_BASE_US1 -#define AT91_USART2 AT91SAM9G45_BASE_US2 -#define AT91_USART3 AT91SAM9G45_BASE_US3 +#define ATMEL_BASE_UDPHS 0xfff78000 +#define ATMEL_BASE_TC0 0xfff7c000 +#define ATMEL_BASE_TC1 0xfff7c040 +#define ATMEL_BASE_TC2 0xfff7c080 +#define ATMEL_BASE_MCI0 0xfff80000 +#define ATMEL_BASE_TWI0 0xfff84000 +#define ATMEL_BASE_TWI1 0xfff88000 +#define ATMEL_BASE_USART0 0xfff8c000 +#define ATMEL_BASE_USART1 0xfff90000 +#define ATMEL_BASE_USART2 0xfff94000 +#define ATMEL_BASE_USART3 0xfff98000 +#define ATMEL_BASE_SSC0 0xfff9c000 +#define ATMEL_BASE_SSC1 0xfffa0000 +#define ATMEL_BASE_SPI0 0xfffa4000 +#define ATMEL_BASE_SPI1 0xfffa8000 +#define ATMEL_BASE_AC97C 0xfffac000 +#define ATMEL_BASE_TSC 0xfffb0000 +#define ATMEL_BASE_ISI 0xfffb4000 +#define ATMEL_BASE_PWMC 0xfffb8000 +#define ATMEL_BASE_EMAC 0xfffbc000 +#define ATMEL_BASE_AES 0xfffc0000 +#define ATMEL_BASE_TDES 0xfffc4000 +#define ATMEL_BASE_SHA 0xfffc8000 +#define ATMEL_BASE_TRNG 0xfffcc000 +#define ATMEL_BASE_MCI1 0xfffd0000 +#define ATMEL_BASE_TC3 0xfffd4000 +#define ATMEL_BASE_TC4 0xfffd4040 +#define ATMEL_BASE_TC5 0xfffd4080 +/* Reserved: 0xfffd8000 - 0xffffe1ff */ -#endif +/* + * System Peripherals physical base addresses. + */ +#define ATMEL_BASE_SYS 0xffffe200 +#define ATMEL_BASE_ECC 0xffffe200 +#define ATMEL_BASE_DDRSDRC1 0xffffe400 +#define ATMEL_BASE_DDRSDRC0 0xffffe600 +#define ATMEL_BASE_SMC 0xffffe800 +#define ATMEL_BASE_MATRIX 0xffffea00 +#define ATMEL_BASE_DMA 0xffffec00 +#define ATMEL_BASE_DBGU 0xffffee00 +#define ATMEL_BASE_AIC 0xfffff000 +#define ATMEL_BASE_PIOA 0xfffff200 +#define ATMEL_BASE_PIOB 0xfffff400 +#define ATMEL_BASE_PIOC 0xfffff600 +#define ATMEL_BASE_PIOD 0xfffff800 +#define ATMEL_BASE_PIOE 0xfffffa00 +#define ATMEL_BASE_PMC 0xfffffc00 +#define ATMEL_BASE_RSTC 0xfffffd00 +#define ATMEL_BASE_SHDWN 0xfffffd10 +#define ATMEL_BASE_RTT 0xfffffd20 +#define ATMEL_BASE_PIT 0xfffffd30 +#define ATMEL_BASE_WDT 0xfffffd40 +#define ATMEL_BASE_GPBR 0xfffffd60 +#define ATMEL_BASE_RTC 0xfffffdb0 +/* Reserved: 0xfffffdc0 - 0xffffffff */ /* * Internal Memory. */ -#define AT91SAM9G45_SRAM_BASE 0x00300000 /* Internal SRAM base address */ -#define AT91SAM9G45_SRAM_SIZE SZ_64K /* Internal SRAM size (64Kb) */ - -#define AT91SAM9G45_ROM_BASE 0x00400000 /* Internal ROM base address */ -#define AT91SAM9G45_ROM_SIZE SZ_64K /* Internal ROM size (64Kb) */ +#define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */ +#define ATMEL_BASE_ROM 0x00400000 /* Internal ROM base address */ +#define ATMEL_BASE_LCDC 0x00500000 /* LCD Controller */ +#define ATMEL_BASE_UDPHS_FIFO 0x00600000 /* USB Device HS controller */ +#define ATMEL_BASE_HCI 0x00700000 /* USB Host controller (OHCI) */ +#define ATMEL_BASE_EHCI 0x00800000 /* USB Host controller (EHCI) */ +#define ATMEL_BASE_VDEC 0x00900000 /* Video Decoder Controller */ -#define AT91SAM9G45_LCDC_BASE 0x00500000 /* LCD Controller */ -#define AT91SAM9G45_UDPHS_FIFO 0x00600000 /* USB Device HS controller */ -#define AT91SAM9G45_HCI_BASE 0x00700000 /* USB Host controller (OHCI) */ -#define AT91SAM9G45_EHCI_BASE 0x00800000 /* USB Host controller (EHCI) */ -#define AT91SAM9G45_VDEC_BASE 0x00900000 /* Video Decoder Controller */ - -#define CONFIG_DRAM_BASE AT91_CHIPSELECT_6 +/* + * Other misc defines + */ +#define ATMEL_PIO_PORTS 5 /* this SoCs has 5 PIO */ /* * Cpu Name */ -#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9G45" +#define ATMEL_CPU_NAME "AT91SAM9G45" #endif